1. A fabrication method of a transparent conductive electrode, comprising:
forming a sacrificial layer pattern on a substrate having a first region and a second region adjacent to each other, wherein the sacrificial layer pattern is located in the second region, and has an upper sharp corner profile formed on a side adjacent to the first region;
forming a transparent conductive thin-film in the first and second regions of the substrate with the sacrificial layer pattern formed thereon, wherein a thickness ratio of the transparent conductive thin-film to the sacrificial layer pattern is less than or equal to 1:1.5, and the transparent conductive thin-film is disconnected at the upper sharp corner profile of the sacrificial layer pattern, such that at least a part of a side surface of the sacrificial layer pattern facing the first region is exposed; and
removing the sacrificial layer pattern so as to reserve the transparent conductive thin-film in the first region as the transparent conductive electrode.
2. The method according to claim 1, wherein
the sacrificial layer pattern is formed to have a cross section of inverted trapezoid shape.
3. The method according to claim 1, wherein the thickness ratio of the transparent conductive thin-film to the sacrificial layer pattern is between 1:1.5 and 1:3.
4. The method according to claim 1, wherein the removing the sacrificial layer pattern is performed by a wet etching process, and a wet etchant adopted in the wet etching process has an etching selection ratio of the transparent conductive thin-film to the sacrificial layer pattern which is smaller than or equal to 1:20.
5. The method according to claim 4, wherein the wet etchant adopted in the wet etching process has an etching selection ratio of the transparent conductive thin-film to the sacrificial layer pattern which is between 1:20 and 1:200.
6. The method according to claim 1, wherein a material of the transparent conductive thin-film is ITO or IZO.
7. The method according to claim 1, wherein a material of the sacrificial layer pattern comprises a metal nitrogen oxide.
8. The method according to claim 7, wherein the metal nitrogen oxide comprises zinc nitrogen oxide.
9. The method according to claim 2, wherein the wet etchant is a hydrochloric acid solution with a concentration of 0.1%-0.3% and a temperature of 20\xb0 C.-45\xb0 C.
10. A fabrication method of an array substrate, comprising: forming a thin film transistor on a base substrate, and forming a pixel electrode electrically connected to a drain of the thin film transistor, wherein the pixel electrode is fabricated by the fabrication method according claim 1.
11. The method according to claim 10, wherein, in a case that the pixel electrode is formed after forming the thin film transistor, a process temperature for forming the sacrificial layer pattern during fabricating the pixel electrode is less than 200\xb0 C.
12. A fabrication method of an array substrate, comprising: forming a thin film transistor on a base substrate, forming a pixel electrode electrically connected to a drain of the thin film transistor, and forming a common electrode, wherein the pixel electrode and the common electrode are both fabricated by the fabrication method according to claim 1.
13. The method according to claim 12, wherein, in a case that the pixel electrode andor the common electrode areis formed after forming the thin film transistor, a temperature for forming the sacrificial layer pattern during forming the pixel electrode andor the common electrode is less than 200\xb0 C.
14. The method according to claim 2, wherein the thickness ratio of the transparent conductive thin-film to the sacrificial layer pattern is between 1:1.5 and 1:3.
15. The method according to claim 2, wherein the removing the sacrificial layer pattern is performed by a wet etching process, and a wet etchant adopted in the wet etching process has an etching selection ratio of the transparent conductive thin-film to the sacrificial layer pattern which is smaller than or equal to 1:20.
16. The method according to claim 3, wherein the removing the sacrificial layer pattern is performed by a wet etching process, and a wet etchant adopted in the wet etching process has an etching selection ratio of the transparent conductive thin-film to the sacrificial layer pattern which is smaller than or equal to 1:20.
17. The method according to claim 2, wherein a material of the transparent conductive thin-film is ITO or IZO.
18. The method according to claim 3, wherein a material of the transparent conductive thin-film is ITO or IZO.
19. The method according to claim 4, wherein a material of the transparent conductive thin-film is ITO or IZO.
20. The method according to claim 5, wherein a material of the transparent conductive thin-film is ITO or IZO.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix, the memory cells arranged in each column being coupled in series to configure a NAND unit, the NAND unit being coupled to a bit line and a source line, and the memory cells arranged in each row being coupled to a word line;
a control circuit which controls the potentials of the word line, the bit line, the source line and a well containing the memory cells;
a first voltage generating circuit configured to generate a first voltage; and
a second voltage generating circuit configured to generate a second voltage,
wherein, when reading data from a memory cell, the control circuit supplies the first voltage generated by the first voltage generating circuit to the source line, supplies the second voltage generated by the second voltage generating circuit to the bit line, supplies a first predetermined voltage for reading data of memory cells to a selected word line, and supplies a second predetermined voltage for setting memory cells to off state to an unselected word line.
2. The semiconductor memory device according to claim 1, wherein when reading data from the memory cells, the control circuit supplies the first voltage generated by the first voltage generating circuit to the well.
3. The semiconductor memory device according to claim 1, wherein the NAND unit has a select transistor, and when reading data from the memory cell, the control circuit supplies the first voltage generated by the first voltage generating circuit to the well, and supplies a third predetermined voltage for setting the select transistor in an on-state to a gate of the select transistor.