1. An inspection machine for pressure testing a glass bottle including
a pressure head locatable on the top of a water filled glass bottle,
an PSIsecond air supply connected to said pressure head for subjecting the bottle to pressure increasing at a linear rate,
a control,
a pressure sensor for sensing the pressure within the pressure head and supplying the sensed pressure to said control,
said control for
operating said PSIsecond air supply until a desired maximum pressure is sensed by said pressure sensor in a bottle that does not burst or leak,
determining when a bottle bursts or leaks,
determining, when a bottle bursts or leaks, the slope of the pressure curve as it falls off from a maximum value below said desired maximum pressure,
identifying the bottle as a burst bottle when said slope exceeds a defined slope,
identifying the bottle as a leaker when said slope is less than the defined slope, and
when in \u201cN\u201d successive bottles, the pressure curve falls off from a maximum value and said slope is less than said defined slope, identify a maintenance problem.
2. An inspection machine for pressure testing a glass bottle according to claim 1, wherein said control for determining when the bottle bursts or leaks comprises means for determining that the pressure curve has a linear portion followed by a portion that departs from linear.
3. An inspection machine for pressure testing a glass bottle according to claim 2, wherein said control for determining the slope of the pressure curve as its falls from a maximum value includes time delay means operable when the linear portion transitions to the portion that departs from linear.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. (canceled)
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. (canceled)
17. (canceled)
18. (canceled)
19. (canceled)
20. (canceled)
21. (canceled)
22. A SOI structure made by the method comprising:
providing a first substrate with a lightly doped impurity region containing a highly doped impurity region therein;
forming a trench in the substrate, wherein the depth of the trench is deeper than the highly doped impurity region and shallower than the lightly doped impurity region;
providing a substantially planar insulating layer on an upper surface of the first substrate containing the trench;
providing a second substrate on the insulating layer; and
removing a portion of the first substrate sufficient to expose the trench.
23. A SOI structure made by the method comprising:
providing a first substrate with a lightly doped impurity region containing a highly doped impurity region therein;
forming a trench in the substrate, wherein the depth of the trench is deeper than the highly doped impurity region and shallower than the lightly doped impurity region;
forming a second trench in the first trench by forming a first insulating layer on the surface of the first substrate containing the first trench;
forming a polycrystalline silicon layer to fill the second trench;
forming a second insulating layer on the polycrystalline silicon layer;
providing a second substrate on the second insulating layer; and
removing a portion of the first substrate to expose the first insulating layer.
24. (canceled)
25. (canceled)
26. A semiconductor device made by the method comprising:
providing a first substrate with a lightly doped impurity region containing a highly doped impurity region therein;
forming a trench in the substrate, wherein the depth of the trench is deeper than the highly doped impurity region and shallower than the lightly doped impurity region;
providing substantially planar insulating layer on an upper surface of the first substrate containing the trench;
providing a second substrate on the insulating layer; and
removing a portion of the first substrate sufficient to expose the trench.
27. A semiconductor device made by the method comprising:
providing a first substrate with a lightly doped impurity region containing a highly doped impurity region therein;
forming a trench in the substrate, wherein the depth of the trench is deeper than the highly doped impurity region and shallower than the lightly doped impurity region;
forming a second trench in the first trench by forming a first insulating layer on the surface of the first substrate containing the first trench;
forming a polycrystalline silicon layer to fill the second trench;
forming a second insulating layer on the polycrystalline silicon layer;
providing a second substrate on the second insulating layer; and
removing a portion of the first substrate to expose the first insulating layer.
28. (canceled)
29. (canceled)
30. (canceled)
31. The SOI structure of claim 22, wherein the substantially planar insulating layer is provided by deposition and then by chemical mechanical polishing.
32. The SOI structure of claim 22, wherein the break-down voltage of a semiconductor device using the SOI structure can be controlled using the height of the trench.
33. The SOI structure of claim 22, wherein the second substrate does not comprise an epitaxial layer.
34. The device of claim 26, wherein the substantially planar insulating layer is provided by deposition and then by chemical mechanical polishing.
35. The device of claim 26, wherein the break-down voltage is controlled using the height of the trench.
36. The device of claim 26, wherein the second substrate does not comprise an epitaxial layer.
37. The SOI structure of claim 23, further comprising a process of planarizing the upper surface of the polycrystalline silicon layer.
38. The SOI structure of claim 37, wherein the process of planarizing is performed by a chemical mechanical polishing.
39. The SOI structure of claim 23, wherein the break-down voltage of a device using the SOI structure can be controlled using the height of the trench.
40. The SOI structure of claim 23, wherein the second substrate does not comprise an epitaxial layer.
41. The device of claim 27, further comprising a process of planarizing the upper surface of the polycrystalline silicon layer.
42. The device of claim 41, wherein the process of planarizing is performed by a chemical mechanical polishing.
43. The device of claim 27, wherein the break-down voltage is controlled using the height of the trench.
44. The device of claim 27, wherein the second substrate does not comprise an epitaxial layer.
45. A SOI structure, comprising:
a substrate not containing an epitaxial layer;
a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity;
a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity; and
an insulating layer isolating the substrate, first dopant region, and second dopant region.
46. The SOI structure of claim 45, wherein the break-down voltage of a device using the SOI structure can be controlled using the depths of the first and second dopant regions.
47. The SOI structure of claim 45, wherein the first and second dopant regions have an upper surface substantially planar with an upper surface of the insulating layer.
48. The SOI structure of claim 45, wherein the first dopant region forms part of a PNP transistor and the second region forms part of a NPN transistor.
49. The SOI structure of claim 48, wherein the SOI structure is part of a complementary bipolar transistor device.
50. A SOI structure, comprising:
a substrate not containing an epitaxial layer;
a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity;
a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity; and
an insulating layer isolating the substrate, first dopant region, and second dopant region, the insulating layer containing a conductive layer.
51. The SOI structure of claim 50, wherein the conductive layer has a substantially planar surface.
52. The SOI structure of claim 50, wherein the break-down voltage of a device using the SOI structure can be controlled using the depths of the first and second dopant regions.
53. The SOI structure of claim 50, wherein the first and second dopant regions have an upper surface substantially planar with an upper surface of the insulating layer.
54. The SOI structure of claim 50, wherein the first dopant region forms part of a PNP transistor and the second region forms part of a NPN transistor.
55. The SOI structure of claim 54, wherein the SOI structure is part of a complementary bipolar transistor device.