What is claimed is:
1. A method of etching an organic film, comprising the steps of:
forming an intermediate layer and a patterned resist layer on an organic film;
etching the intermediate layer exposed from the resist layer; and
then etching the organic film using a plasma of a gas,
wherein the intermediate layer comprises a layer comprised of a metal or metal compound.
2. The method according to claim 1, wherein the metal is aluminium, copper, titanium, cobalt, tantalum, platinum, chromium or tungsten.
3. The method according to claim 1, wherein the metal compound is titanium nitride, tungsten nitride or tantalum nitride.
4. The method according to claim 1, wherein the gas is N2, H2, a mixed gas of N2 and H2, NH3 or N2H4.
5. The method according to claim 1, wherein the plasma is a surface-wave interfered plasma.
6. The method according to claim 1, wherein the organic film is a polyaryl ether or fluorinated polyaryl ether.
7. The method according to claim 1, wherein the organic film comprises a low-dielectric-constant material having a lower dielectric constant than silicon oxide.
8. The method according to claim 1, wherein the organic film comprises a low-dielectric-constant material having a lower dielectric constant than silicon oxide, and the gas is a gas containing at least one of nitrogen and hydrogen.
9. The method according to claim 1, wherein the intermediate layer comprises an inorganic insulating layer in contact with the organic film.
10. A method of etching an organic film, comprising the steps of:
forming an intermediate layer and a patterned resist layer on an organic low-dielectric-constant film;
etching the intermediate layer exposed from the resist layer; and
then etching the organic low-dielectric-constant film using a plasma of a gas containing either of nitrogen and hydrogen,
wherein the intermediate layer comprises a layer comprised of a metal or metal nitride.
11. A method of producing an element, comprising the steps of:
forming an organic insulating film, an intermediate layer and a patterned resist layer on a substrate;
etching the intermediate layer exposed from the resist layer, and then etching the organic insulating film using a plasma of a gas; and
filling with a conductor a portion where the organic insulating film is etched away,
wherein the intermediate layer comprises a layer comprised of a metal or metal compound.
12. The method according to claim 11, further comprising, after the filling with the conductor, the step of removing the layer comprised of the metal or metal compound.
13. The method according to claim 11, wherein the metal is aluminium, copper, titanium, cobalt, tantalum, platinum, chromium or tungsten.
14. The method according to claim 11, wherein the metal compound is titanium nitride, tungsten nitride or tantalum nitride.
15. The method according to claim 11, wherein the gas is N2, H2, a mixed gas of N2 and H2, NH3 or N2H4.
16. The method according to claim 11, wherein the plasma is a surface-wave interfered plasma.
17. The method according to claim 11, wherein the organic insulating film is a polyaryl ether or fluorinated polyaryl ether.
18. The method according to claim 11, wherein the organic insulating film comprises a low-dielectric-constant material having a lower dielectric constant than silicon oxide.
19. The method according to claim 11, wherein the organic insulating film comprises a low-dielectric-constant material having a lower dielectric constant than silicon oxide, and the gas is a gas containing at least one of nitrogen and hydrogen.
20. The method according to claim 11, wherein the intermediate layer comprises an inorganic insulating layer in contact with the organic insulating film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A verification apparatus comprising:
a. an authentication module accessed via a trusted firmware layer and adapted to verify a cryptographic key; and
b. a validation module responsive to verification of said key, wherein said key is adapted to restrict access of an application to a hardware resource.
2. The apparatus of claim 1, wherein said key is computed from a value previously obtained from said authentication module.
3. The apparatus of claim 2, wherein said previously obtained value is a timestamp.
4. The apparatus of claim 1, wherein said authentication module is implemented in software as part of the trusted firmware layer.
5. The apparatus of claim 1, wherein said trusted firmware layer controls restricted access to said hardware resource.
6. The apparatus of claim 1, wherein said authentication module is adapted to utilize a hardware register.
7. The apparatus of claim 6, further comprising a first hardware register to hold said key and a second register to communicate with said hardware resource.
8. The apparatus of claim 7, further comprising a third hardware register to present a value from which the key must be computed.
9. The apparatus of claim 1, wherein said hardware resource is selected from the group consisting of: a graphics accelerator, a floating point accelerator, a high resolution frame buffer, and combinations thereof.
10. The apparatus of claim 1, wherein said hardware resource is a central processing unit of a game set.
11. A method for restricting access to computer hardware comprising:
presenting a cryptographic key to an authentication module;
accessing said authentication module through a trusted firmware layer;
validating said key; and
limiting access of an application to said computer hardware in response to key validation.
12. The method of claim 11, wherein the step of validating said key includes presenting said key through a firmware call.
13. The method of claim 12, wherein said firmware call is selected from the group consisting of: a software interrupt and a protected procedure call.
14. The method of claim 11, wherein the step of validating said key includes writing a valid key to a hardware register of said computer hardware.
15. The method of claims 11, wherein hardware is selected from the group consisting of: a graphics accelerator, a floating-point accelerator, a high-resolution frame buffer, and combinations thereof.
16. The method of claim 11, wherein said computer hardware is a central processing unit of a game set.
17. An article comprising:
a computer-readable signal-bearing medium;
a cryptographic key adapted to be verified through a trusted firmware layer;
a verification module adapted to respond to said key; and
computer hardware adapted to receive limited access in response to verification of said key.
18. The article of claim 17, wherein the medium is selected from: a recordable data storage and a modulated carrier signal.
19. The article of claim 17, wherein key verification is implemented in software as part of the trusted firmware layer.
20. The article of claim 17, wherein key verification is implemented in a hardware register.
21. The article of claim 17, wherein limited access to said hardware is responsive to presentation of said key to said verification module.
22. The article of claim 17, wherein said hardware is selected from the group consisting of: a graphics accelerator, a floating point accelerator, a high resolution frame buffer, and combinations thereof.
23. The article of claim 17, wherein said hardware is a central processing unit of a game set.
24. A game set comprising:
a. a central processing unit having an acceleration hardware resource;
b. an authentication module accessed via a trusted firmware layer and adapted to verify a cryptographic key; and
b. a validation module responsive to verification of said key, wherein said key is adapted to restrict access of an application to said hardware resource.
25. The game set of claim 24, wherein said key is computed from a value previously obtained from said authentication module.
26. The game set of claim 24, wherein said authentication module is implemented in software as part of the trusted firmware layer.
27. The game set of claim 24, wherein said authentication module is adapted to utilize a hardware register.
28. The game set of claim 27, further comprising a first hardware register to hold said key and a second hardware register to communicate with said hardware resource.