1. A light emitting device, comprising:
a III-nitride light emitting diode (LED) comprised of an active III-nitride layer that emits light formed between n-type and p-type III-nitride layers, wherein:
the III-nitride layers are semi-polar or non-polar III-nitride layers;
at least one surface of the LED is a textured surface;
the textured surface is comprised of at least one conical feature having at least one sloped sidewall that reflects or transmits at least one light ray incident thereon from inside the conical feature; and
the sidewall is inclined, such that each time the light ray is reflected, there is an increased chance of the light ray being transmitted through the sidewall.
2. The device of claim 1, wherein:
the textured surface forms an interface with an external medium;
the conical feature with the sloped sidewall transmits the light ray into the external medium at the interface and reflects the light ray at the interface; and
the reflected light ray, after undergoing subsequent reflections inside the conical feature, has an increased incidence angle at the interface and consequently an increased chance of being transmitted to the external medium.
3. The device of claim 2, wherein the external medium has a refractive index less than the III-nitride layers.
4. The device of claim 1, wherein:
the sidewall is inclined, such that each time the light ray is reflected, an angle of incidence of the light ray relative to a surface normal of the sidewall decreases;
when the angle of incidence of the light ray is smaller than a critical angle, the light ray’s transmission through the sidewall is increased; and
when the angle of incidence of the light ray is at least equal to the critical angle, the light ray is reflected by the sidewall.
5. The device of claim 4, wherein the sidewall is inclined such that the light ray escapes the conical feature when the angle of incidence is near normal.
6. The device of claim 1, wherein the conical features tile up most of the textured surface.
7. The device of claim 1, wherein the LED includes a substrate, and the textured surface is a surface of the substrate opposite the LED’s growth front.
8. The device of claim 1, wherein the light is extracted from both sides of the LED.
9. A method for fabricating a light emitting device, comprising:
creating a III-nitride light emitting diode (LED) comprised of a III-nitride active layer that emits light formed between n-type and p-type III-nitride layers, wherein:
the III-nitride layers are semi-polar or non-polar III-nitride layers;
at least one surface of the LED is a textured surface;
the textured surface is comprised of at least one conical feature having at least one sloped sidewall that reflects or transmits at least one light ray incident thereon from inside the conical feature; and
the sidewall is inclined, such that each time the light ray is reflected, there is an increased chance of the light ray being transmitted through the sidewall.
10. The method of claim 9, wherein:
the textured surface forms an interface with an external medium;
the conical feature with the sloped sidewall transmits the light ray into the external medium at the interface and reflects the light ray at the interface; and
the reflected light ray, after undergoing subsequent reflections inside the conical feature, has an increased incidence angle at the interface and consequently an increased chance of being transmitted to the external medium.
11. The method of claim 10, wherein the external medium has a refractive index less than the III-nitride layers.
12. The method of claim 9, wherein:
the sidewall is inclined, such that each time the light ray is reflected, an angle of incidence of the light ray relative to a surface normal of the sidewall decreases;
when the angle of incidence of the light ray is smaller than a critical angle, the light ray’s transmission through the sidewall is increased; and
when the angle of incidence of the light ray is at least equal to the critical angle, the light ray is reflected by the sidewall.
13. The method of claim 12, wherein the sidewall is inclined such that the light ray escapes the conical feature when the angle of incidence is near normal.
14. The method of claim 9, wherein the conical features tile up most of the textured surface.
15. The method of claim 9, wherein the LED includes a substrate, and the textured surface is a surface of the substrate opposite the LED’s growth front.
16. The method of claim 9, wherein the light is extracted from both sides of the LED.
17. The method of claim 9, wherein the textured surface is formed by photolithography or nano-imprinting followed by etching.
18. The method of claim 9, wherein the textured surface is formed using a plasma assisted chemical etching.
19. The method of claim 9, wherein the textured surface is formed using a photo-enhanced chemical (PEC) etching.
20. A method for emitting light, comprising:
emitting light from a III-nitride light emitting diode (LED) comprised of a III-nitride active layer formed between n-type and p-type III-nitride layers, wherein:
the III-nitride layers are semi-polar or non-polar III-nitride layers;
at least one surface of the LED is a textured surface;
the textured surface is comprised of at least one conical feature having at least one sloped sidewall that reflects or transmits at least one light ray incident thereon from inside the conical feature; and
the sidewall is inclined, such that each time the light ray is reflected, there is an increased chance of the light ray being transmitted through the sidewall.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An SRAM device, comprising:
a hierarchical grouping of memory cells; and
biasing circuitry, coupled to said hierarchical grouping of memory cells, having a switch configured to bias a subset of said hierarchical grouping of memory cells by coupling a local bitline of said subset to a global bitline of said hierarchical grouping of memory cells based on a memory address associated therewith, and having a unique footer for at least one subset of said subset configured to bias said at least one subset in an active mode by coupling said at least one subset to ground based on said memory address.
2. The SRAM device as recited in claim 1 further comprising a plurality of memory cell hierarchies and said hierarchical grouping of memory cells is one of said plurality.
3. The SRAM device as recited in claim 1 further comprising multiple subsets of said subset of said hierarchical grouping of memory cells.
4. The SRAM device as recited in claim 1 wherein said subset of said hierarchical grouping of memory cells is one of a plurality of subsets and said biasing circuitry is configured to bias only said subset of said hierarchical grouping of memory cells in an active mode.
5. The SRAM device as recited in claim 1 wherein said switch is configured to operate based on a decoded portion of said memory address.
6. The SRAM device as recited in claim 1 wherein said biasing circuitry employs a decode signal of said memory address.
7. The SRAM device as recited in claim 1 wherein said biasing circuitry biases said subset of said hierarchical grouping of memory cells based on a biasing condition.
8. The SRAM device as recited in claim 1 wherein said biasing circuitry biases said subset of said hierarchical grouping of memory cells into a biasing condition selected from the group consisting of:
an unselected group of an unselected block,
an unselected group of a selected block, and
a selected group of a selected block.
9. The SRAM device as recited in claim 1 wherein said biasing circuitry employs a low drop-out (LDO) voltage regulator.
10. A method of placing a portion of memory cells of an SRAM device in an active mode, comprising:
receiving a memory address associated with a hierarchical grouping of memory cells; and
biasing a subset of said hierarchical grouping of memory cells by controlling a switch based on said memory address to couple a local bitline of said subset to a global bitline of said hierarchical grouping of memory cells and by controlling a unique footer of at least one subset of said subset to couple said at least one subset to ground based on said memory address.
11. The method as recited in claim 10 wherein said hierarchical grouping of memory cells is one of a plurality of memory cell hierarchies.
12. The method as recited in claim 10 wherein said subset of said hierarchical grouping of memory cells includes multiple subsets.
13. The method as recited in claim 10 wherein said subset is one of a plurality of subsets, further comprising biasing only said subset in an active mode.
14. The method as recited in claim 10 wherein said biasing further includes operating a unique header of said at least one subset.
15. The method as recited in claim 10 wherein said biasing includes employing a decode signal of said memory address.
16. The method as recited in claim 10 wherein said biasing includes biasing said subset based on a biasing condition.
17. The method as recited in claim 10 wherein said biasing includes biasing said subset into a biasing condition selected from the group consisting of:
an unselected group of an unselected block,
an unselected group of a selected block, and
a selected group of a selected block.
18. The method as recited in claim 10 wherein said biasing employs a low drop-out (LDO) voltage regulator.