1. A method of manufacture of an integrated circuit packaging system comprising:
providing an interposer having an interposer first side and an interposer second side opposing the interposer first side;
mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer;
connecting first interconnects between the active side and the interposer first side, the first interconnects are connected to integrated circuit pads and have a first density on the interposer first side, the integrated circuit pads have a pad pitch;
mounting the interposer over a package carrier with the interposer first side facing the package carrier;
connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density is approximately the same as the first density;
mounting an integrated circuit interconnect over the package carrier, the integrated circuit interconnect has a bump pitch, the pad pitch is three to four times tighter than the bump pitch, the integrated circuit has a higher inputoutput (IO) density than that of the integrated circuit interconnect;
connecting the integrated circuit interconnect between the active side of the integrated circuit and the package carrier to provide a shorter electrical signal path between the integrated circuit and the package carrier than the first interconnects and the second interconnects; and
forming an encapsulation over the package carrier covering the interposer and the second interconnects.
2. The method as claimed in claim 1 wherein connecting the first interconnects includes connecting the first interconnects at an interposer peripheral region of the interposer.
3. The method as claimed in claim 1 wherein connecting the second interconnects includes connecting the second interconnects at an interposer peripheral region of the interposer.
4. The method as claimed in claim 1 wherein:
connecting the integrated circuit interconnect includes connecting the integrated circuit interconnect in an array configuration;
connecting the first interconnects between the active side and the interposer first side includes connecting the first interconnects to the integrated circuit peripheral region and the interposer first side; and
connecting the second interconnects having the second density at least three times greater than that of the integrated circuit interconnect.
5. The method as claimed in claim 1 wherein:
mounting the integrated circuit includes mounting the integrated circuit having an integrated circuit interior region, the integrated circuit interconnect at the integrated circuit interior region; and
connecting the first interconnects includes connecting the first interconnects adjacent to the integrated circuit interconnect.
6. The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation covering the integrated circuit interconnect and the first interconnects.
7. The method as claimed in claim 1 further comprising forming an underfill covering the integrated circuit interconnect and the first interconnects.
8. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting a high density flip chip to the interposer first side.
9. An integrated circuit packaging system comprising:
an interposer having an interposer first side and an interposer second side opposing the interposer first side;
an integrated circuit mounted to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer;
first interconnects between the active side and the interposer first side, the first interconnects are connected to integrated circuit pads and have a first density on the interposer first side, the integrated circuit pads have a pad pitch;
a package carrier with the interposer thereover, the interposer first side facing the package carrier;
second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density is approximately the same as the first density;
the integrated circuit having an integrated circuit interconnect, the integrated circuit interconnect having a bump pitch disposed between the active side of the integrated circuit and the package carrier, the pad pitch is three to four times tighter than the bump pitch, the integrated circuit has a higher inputoutput (IO) density than that of the integrated circuit interconnect, the integrated circuit interconnect is configured to provide a shorter electrical signal path between the integrated circuit and the package carrier than the first interconnects and the second interconnects; and
an encapsulation over the package carrier covering the interposer and the second interconnects.
10. The system as claimed in claim 9 wherein the first interconnects are at an interposer peripheral region of the interposer.
11. The system as claimed in claim 9 wherein the second interconnects are at an interposer peripheral region of the interposer.
12. The system as claimed in claim 9 wherein:
the integrated circuit has an integrated circuit interconnect facing away from the interposer; and
the package carrier with the interposer thereover includes the integrated circuit interconnect mounted over the package carrier.
13. The system as claimed in claim 9 wherein:
the integrated circuit interconnect is in an array configuration;
the first interconnects between the active side and the interposer first side is connected to the integrated circuit peripheral region and the interposer first side; and
the second interconnects has the second density at least three times greater than that of the integrated circuit interconnect.
14. The system as claimed in claim 9 wherein:
the integrated circuit has an integrated circuit interior region, the integrated circuit interconnect at the integrated circuit interior region; and
the first interconnects are adjacent to the integrated circuit interconnect.
15. The system as claimed in claim 9 wherein the encapsulation covers the integrated circuit interconnect and the first interconnects.
16. The system as claimed in claim 9 further comprising an underfill covering the integrated circuit interconnect and the first interconnects.
17. The system as claimed in claim 9 wherein the integrated circuit is a high density flip chip mounted to the interposer first side.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A catalytic chemical reaction selected from oxidation, hydrogenation, dehydrogenation, oxidative-hydrogenation, and oxidative-dehydrogenation which is catalyzed by a catalyst composition comprised of graphitic nanofibers which nanofibers are comprised of a plurality of graphite platelets aligned at an angle from about 1\xb0 to about 90\xb0 with respect to the longitudinal axis of the nanofibers and which nanofibers have a crystallinity greater than about 90%, which method comprises heat treating said nanofibers in an inert gas environment at temperatures from about 2300\xb0 C. to about 3000\xb0 C.
2. The catalytic chemical reaction of claim 1 which is a oxidative-hydrogenation reaction.
3. The catalytic chemical reaction of claim 2 which is the oxidative-hydrogenation reaction of ethylbenzene to styrene.
4. The catalytic chemical reaction of claim 1 wherein the platelets are aligned substantially 90\xb0 with respect to the longitudinal axis of the nanofiber.
5. The catalytic chemical reaction of claim 1 wherein the platelets are aligned at angle from about 30\xb0 to about 60\xb0 with respect to the longitudinal axis of the nanofibers.
6. The catalytic chemical reaction of claim 1 wherein the inert gas is selected from helium and argon.
7. The catalytic chemical reaction of claim 3 wherein the platelets are aligned substantially 90\xb0 with respect to the longitudinal axis of the nanofiber.
8. The catalytic chemical reaction of claim 3 wherein the platelets are aligned at angle from about 30\xb0 to about 60\xb0 with respect to the longitudinal axis of the nanofibers.
9. The catalytic chemical reaction of claim 3 wherein said graphitic nanofibers are intercalated with an intercalation component selected from the group consisting of Li, Na, K, Rb, Cs, Br2, Cl2, F2, ICl, ICl3, H2SO4, HNO3, H2SeO4, HClO4, H3PO4, H4P2O7, H3AsO4, HF, CrO2Cl2, CrO2F2, UO2Cl2, FeCl, CuCl2, BCl3, AlCl3, CoCl3, RuCl3, RhCl3, PdCl4, PtCl4, Cr2O3, Sb2O3, MoO3, Sb2S3, CuS, FeS2 Cr2S3, V2S3 and WS2.