1. A polyester film wherein an adhesive layer comprising
a thermoplastic elastomer including a monovinyl substituted aromatic hydrocarbon and a conjugated diene,
a polyester resin having a glass transition temperature of 35 to 150\xb0 C. and a carboxyl group content of 10 to 100 mg KOHg, and
a compatibilizer compatibilizing the thermoplastic elastomer and the polyester resin with each other, the compatibilizer being selected from polyvinyl acetate, acrylic resin and styrene-acryl copolymer and having a glass transition temperature of 35 to 150\xb0 C., is laminated on a polyester substrate.
2. The polyester film according to claim 1, being a base film for use in a photosensitive resin printing plate.
3. A photosensitive resin structure wherein a photosensitive resin layer is disposed on the adhesive layer of the polyester film according to claim 2.
4. The photosensitive resin structure according to claim 3, wherein the photosensitive resin layer comprises a thermoplastic elastomer, an ethylenically unsaturated compound and a photopolymerization initiator.
5. The photosensitive resin structure according to claim 4, wherein the thermoplastic elastomer included in the photosensitive resin layer comprises a first polymer block including a conjugated diene unit or a hydrogenated conjugated diene unit and a second polymer block including a vinyl aromatic hydrocarbon unit.
6. The photosensitive resin structure according to claim 4, wherein the thermoplastic elastomer included in the photosensitive resin layer comprises a first polymer block including a butadiene unit or a hydrogenated butadiene unit and a second polymer block including a vinyl aromatic hydrocarbon unit.
7. A photosensitive resin structure wherein a photosensitive resin layer is disposed on the adhesive layer of the polyester film according to claim 1.
8. The photosensitive resin structure according to claim 7, wherein the photosensitive resin layer comprises a thermoplastic elastomer, an ethylenically unsaturated compound and a photopolymerization initiator.
9. The photosensitive resin structure according to claim 8, wherein the thermoplastic elastomer included in the photosensitive resin layer comprises a first polymer block including a conjugated diene unit or a hydrogenated conjugated diene unit and a second polymer block including a vinyl aromatic hydrocarbon unit.
10. The photosensitive resin structure according to claim 8, wherein the thermoplastic elastomer included in the photosensitive resin layer comprises a first polymer block including a butadiene unit or a hydrogenated butadiene unit and a second polymer block including a vinyl aromatic hydrocarbon unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated semiconductor device, comprising:
a substrate of a first conductivity type;
a buried layer located over the substrate;
an isolated region located over a first portion of the buried layer;
an isolation trench located around the isolated region; and
a punch-through structure located around at least a portion of the isolation trench, the punch-through structure including:
a second portion of the buried layer,
a first region located over the second portion of the buried layer, the first region having the first conductivity type, and
a second region located over the first region, the second region having a second conductivity type.
2. The device of claim 1, wherein, when the isolated region is set to a greater than zero potential with respect to the substrate, a voltage across the second portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.
3. The device of claim 1, including a second isolation trench located around the punch-through structure.
4. The device of claim 3, including a second punch-through structure located around at least a portion of the second isolation trench, the second punch-through structure including a third portion of the buried layer.
5. The device of claim 4, wherein, when the isolated region is set to the greater than zero potential with respect to the substrate, a voltage across the third portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.
6. The device of claim 4, wherein the second punch-through structure includes:
a third region located over the third portion of the buried layer, the third region having the first conductivity type, and
a fourth region located over the third region, the fourth region having the second conductivity type
7. The device of claim 6, wherein a depth of the first region of the first punch-through structure is greater than a depth of the third region of the second punch-through structure.
8. The device of claim 4, including a third isolation trench located around the second punch-through structure.
9. The device of claim 1, including a polysilicon material disposed within the isolation trench.
10. The device of claim 9, including an oxide located around the polysilicon material.
11. The device of claim 10, wherein the punch-through structure is configured to pull-up a potential of the polysilicon material disposed within the isolation trench when the isolated region is set to the greater than zero potential with respect to the substrate.
12. The device of claim 1, including a transistor, a resistor, a diode, or a capacitor located at least partially within the isolated region.
13. The device of claim 1, including an insulation region located within the isolated region, the insulation region having a conductivity type being the same as a conductivity type of the buried layer.
14. A method, comprising:
forming a buried layer over a substrate of a first conductivity type;
forming an isolation trench around an isolated region, the isolated region being disposed over a first portion of the buried layer; and
forming a punch-through structure around at least a portion of the isolation trench by:
forming a first region over a second portion of the buried layer, the first region having the first conductivity type, and
forming a second region located over the first region, the second region having a second conductivity type.
15. The method of claim 14, wherein, when the isolated region is set to a greater than zero potential with respect to the substrate, a voltage across the second portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.
16. The method of claim 14, including forming a second isolation trench around the punch-through structure.
17. The method of claim 16, including forming a second punch-through structure around the second isolation trench, the second punch-through structure including a third portion of the buried layer.
18. The method of claim 17, wherein, when the isolated region is set to the greater than zero potential with respect to the substrate, a voltage across the third portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.
19. The method of claim 17, wherein forming the second punch-through structure:
forming a third region over the third portion of the buried layer, the third region having the first conductivity type, and
forming a fourth region over the third region, the fourth region having the second conductivity type
20. The method of claim 19, wherein a depth of the first region of the first punch-through structure is greater than a depth of the third region of the second punch-through structure.