1. A method, comprising:
mapping one or more banks in a memory to a first device for exclusive use; and
mapping one or more other banks in the memory to a second device for exclusive use.
2. The method of claim 1, further comprising mapping one or more other banks in the memory, separate from the one or more banks mapped to the first device for exclusive use and from the one or more banks mapped to the second device for exclusive use, for shared use by the first device and the second device.
3. The method of claim 2, wherein the one or more banks mapped to the first device for exclusive use, the one or more banks mapped to the second device for exclusive use, and the one or more banks mapped to the first device and second device for shared use are the complete set of banks available for use in the memory.
4. The method of claim 2, wherein the one or more banks mapped to the first device for exclusive use, the one or more banks mapped to the second device for exclusive use, arid the one or more banks mapped to the first device and second device for shared use are not the complete set of banks available for use in the memory.
5. The method of claim 1, wherein mapping the banks in the memory occurs during the power on sequence of a computer system that the memory is located within.
6. The method of claim 1, further comprising:
loading an operating system into a portion of the memory mapped to the first device for exclusive use;
once the operating system is loaded, loading one or more processes associated with the first device into a portion of the memory exclusively accessible by the first device; and
loading a device driver process that drives the second device into a portion of the memory exclusively accessible by the second device.
7. A method, comprising:
receiving a memory request from a first device, the memory request containing a first target physical address;
translating the first target physical address to a bank-specific physical address in a first memory bank in a memory device, wherein the first device has exclusive access to the first memory bank;
receiving a memory request from a second device, the memory request containing a second target physical address; and
translating the second target physical address to a bank-specific physical address in a second memory bank in the memory device, wherein the second device has exclusive access to the second memory bank.
8. The method of claim 7, further comprising:
receiving a memory request from the first device, the memory request containing a third target physical address;
translating the third target physical address to a bank-specific physical address in a third memory bank in a memory device, wherein the first device and the second device have shared access to the third memory bank;
receiving a memory request from the second device, the memory request containing a fourth target physical address; and
translating the fourth target physical address to a bank-specific physical address in the third memory bank in the memory device.
9. The method of claim 7, further comprising:
loading an operating system into a portion of the memory exclusively accessible by the first device;
once the operating system is loaded, loading one or more processes associated with the first device into a portion of the memory exclusively accessible by the first device; and
loading a device driver process that drives the second device into a portion of memory exclusively accessible by the second device.
10. The method of claim 7, further comprising, prior to receiving the memory requests:
mapping one or more banks in the memory to the first device for exclusive use; and
mapping one or more other banks in the memory to the second device for exclusive use.
11. A device, comprising a memory controller to:
map one or more banks in a memory to a first device for exclusive use; and
map one or more other banks in the memory to a second device for exclusive use.
12. The device of claim 11, wherein the memory controller maps the banks in the memory during the power on sequence of a computer system that the memory is located within.
13. The device of claim 11, wherein the memory controller is further operable to:
load an operating system into a portion of the memory exclusively accessible by the first device;
once the operating system is loaded, load one or more processes associated with the first device into a portion of the memory exclusively accessible by the first device; and
load a device driver process that drives the second device into a portion of the memory exclusively accessible by the second device.
14. A system, comprising;
a bus;
a first processor coupled to the bus;
a second processor coupled to the bus;
a network interface card coupled to the bus;
a memory coupled to the bus;
a chipset coupled to the bus, the chipset comprising a memory controller and address translation unit to:
receive a memory request from the first processor, the memory request containing a first target physical address;
translate the first target physical address to a bank-specific physical address in a first memory bank in the memory, wherein the first processor has exclusive access to the first memory bank;
receive a memory request from the second processor, the memory request containing a second target physical address; and
translate the second target physical address to a bank-specific physical address in a second memory bank in the memory, wherein the second processor has exclusive access to the second memory bank.
15. The system of claim 14, wherein the memory controller and address translation unit is further operable to:
receive a memory request from the first device, the memory request containing a third target physical address;
translate the third target physical address to a bank-specific physical address in a third memory bank in a memory device, wherein the first device and the second device have shared access to the third memory bank;
receive a memory request from the second device, the memory request containing a fourth target physical address; and
translate the fourth target physical address to a bank-specific physical address in the third memory bank in the memory device.
16. The system of claim 14, wherein the memory controller and address translation unit is further operable to:
load an operating system into a portion of the memory exclusively accessible by the first device;
once the operating system is loaded, load one or more processes associated with the first device into a portion of the memory exclusively accessible by the first device; and
load a device driver process that drives the second device into a portion of memory exclusively accessible by the second device.
17. The system of claim 16, wherein the memory controller and address translation unit is further operable to:
at the time of system power on, map each of the banks in the memory to be exclusively accessible to the first processor, to be exclusively accessible to the second processor, or to be accessible to both the first processor and the second processor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a first contact point of said first metallization structure, a second opening in said passivation layer exposing a second contact point of said first metallization structure;
a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first contact point, a fourth opening in said polymer layer exposing said second contact point, wherein said polymer layer has a thickness of greater than 2 microns; and
a second metallization structure over said passivation layer and over said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises a sputtered metal structure and an electroplated metal structure over said sputtered metal structure.
2. The integrated circuit chip of claim 1, wherein said electroplated metal structure comprises copper.
3. The integrated circuit chip of claim 1, wherein said sputtered metal structure comprises aluminum.
4. The integrated circuit chip of claim 1, wherein said polymer layer comprises polyimide.
5. The integrated circuit chip of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).
6. The integrated circuit chip of claim 1, wherein said thickness is between 2 and 30 microns.
7. The integrated circuit chip of claim 1, wherein said first metallization structure comprises electroplated copper.
8. The integrated circuit chip of claim 1, wherein said first metallization structure comprises aluminum.
9. The integrated circuit chip of claim 1 further comprising a metal bump connected to said first and second contact points through said second metallization structure.
10. The integrated circuit chip of claim 9, wherein said metal bump comprises solder.
11. The integrated circuit chip of claim 1, wherein said second metallization structure comprises a wirebonding interconnect pad connected to said first and second contact points through said first and second openings.
12. The integrated circuit chip of claim 1, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
13. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a second metallization structure over said passivation layer and over said first and second pads, wherein said second metallization structure comprises a third pad connected to said first and second pads through said first and second openings, and wherein said second metallization structure comprises a sputtered metal structure and an electroplated metal structure over said sputtered metal structure; and
a solder bump over said third pad.
14. The integrated circuit chip of claim 13, wherein said electroplated metal structure comprises copper.
15. The integrated circuit chip of claim 13 further comprising a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first pad, and a fourth opening in said polymer layer is over said second pad, and wherein said second metallization structure is over said polymer layer.
16. The integrated circuit chip of claim 15, wherein said polymer layer comprises polyimide.
17. The integrated circuit chip of claim 15, wherein said polymer layer comprises benzocyclobutene (BCB).
18. The integrated circuit chip of claim 15, wherein said polymer layer has a thickness between 2 and 30 microns.
19. The integrated circuit chip of claim 13, wherein said first metallization structure comprises electroplated copper.
20. The integrated circuit chip of claim 13, wherein said first metallization structure comprises aluminum.
21. The integrated circuit chip of claim 13, wherein said sputtered metal structure comprises aluminum.