1. An apparatus comprising:
a memory; and
a seller tool executable by a processor and configured to:
determine a pseudo product group for an item to be listed in an online marketplace having unstructured data;
derive a fair market price for the item using past data from listings in the pseudo product group;
use the fair market price as a reference price in a curve of price elasticity versus price to obtain a price elasticity value; and
recommend a price range to a user for the listing based upon the fair market price and the price elasticity value.
2. The apparatus of claim 1, wherein the unstructured data is historical data that lacks demand information for the item.
3. The apparatus of claim 1, wherein the pseudo product group is one of a plurality of mutually exclusive product categories.
4. The apparatus of claim 1, wherein the user is a seller of the item to be listed.
5. A method comprising:
determining a pseudo product group for an item to be listed in an online marketplace having unstructured data;
deriving a fair market price for the item using past data from listings in the pseudo product group;
using the fair market price as a reference price in a curve of price elasticity versus price to obtain a price elasticity value; and
recommending a price range to a user for the listing based upon the fair market price and the price elasticity value.
6. The method of claim 5, wherein the price range is recommended to the user in a seller tool that is utilized when the user lists the item for sale in the online marketplace.
7. The method of claim 6, wherein the price range is presented to the user in the seller tool next to an input box where the user enters a price at which to sell the item.
8. The method of claim 5, wherein the unstructured data is historical data that lacks demand information for the item.
9. The method of claim 5, wherein the pseudo product group is one of a plurality of mutually exclusive product categories.
10. A non-transitory machine-readable storage medium having embodied thereon instructions executable by one or more machines to perform operations comprising:
determining a plurality of pseudo product groups in an online marketplace;
determining dynamic price elasticity in each of the pseudo product groups;
receiving a proposed change to a search ranking algorithm;
determining, based on the dynamic price elasticity in each pseudo product group affected by the proposed change to the search ranking algorithm, an estimated total revenue impact of the proposed change; and
determining whether or not to implement the proposed change based on the estimated total revenue impact.
11. The non-transitory machine-readable storage medium of claim 10, wherein the operations further comprise:
summing up revenue in each of the pseudo product groups;
computing a revenue weight for each pseudo product group from the revenue; and
deriving a set of queries affected by the proposed change in a search ranking algorithm.
12. The non-transitory machine-readable storage medium of claim 11, wherein the operations further comprise:
for each of the derived set of queries:
determining pseudo product groups that a first preset number of search results from an old search rank algorithm belong to;
determining average sale prices of the top preset number of listings in the determined pseudo product groups for the old search rank algorithm;
determining pseudo product groups that a first preset number of search results from a new search rank algorithm belong to; and
determining average sale prices of the top preset number of listings in the determined pseudo product groups for the new search rank algorithm.
13. The non-transitory machine-readable storage medium of claim 11, wherein the determining an estimated total revenue impact of the proposed change includes:
computing an average sale price and price change across all queries in the derived set of queries;
computing a revenue change in each pseudo product group from the average sale price and price change; and
computing a total revenue impact with revenue weights based on the revenue change.
14. The non-transitory machine-readable storage medium of claim 13, wherein the computing a revenue change uses the formula (1+e_v)*(dP_vP_v), wherein e_v is a dynamic price elasticity, dP_v is the price change and P_v is the average sale price.
15. The non-transitory machine-readable storage medium of claim 13, wherein the computing a total revenue impact with revenue weights uses the formula \u03a3v(1+e)*W_v*dP_vP_v, wherein W_v is the revenue weight for each pseudo product group.
16. The non-transitory machine-readable storage medium of claim 10, wherein the dynamic price elasticity is determined by deriving a fair market price for an item using past data from listings in a pseudo product group and using the fair market price as a reference price in a curve of price elasticity versus price to obtain a price elasticity value.
17. The non-transitory machine-readable storage medium of claim 16, wherein the dynamic price elasticity is determined using unstructured data.
18. The non-transitory machine-readable storage medium of claim 17, wherein the unstructured data is historical data that lacks demand information for an item.
19. The non-transitory machine-readable storage medium of claim 10, wherein the pseudo product groups are a plurality of mutually exclusive product categories.
20. The non-transitory machine-readable storage medium of claim 10, wherein estimated total revenue impact is an estimate of effect on the entire online marketplace.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A gate driver for driving a plurality of gate lines in a liquid crystal display, the gate driver comprising:
a first circuit unit for outputting a first driving signal to one odd gate line of the gate lines, comprising:
a first signal output unit for receiving a first odd start signal and a first input signal to generate the first driving signal; and
a first shift register unit for receiving the first odd start signal and a first clock signal to generate a second odd start signal;
a second circuit unit for outputting a second driving signal to another odd gate line of the gate lines, the second circuit unit electrically coupling to the first circuit unit and comprising:
a second signal output unit for receiving the second odd start signal and the first input signal to generate the second driving signal; and
a second shift register unit for receiving the second odd start signal and the first clock signal to generate a third odd start signal;
a third circuit unit for outputting a third driving signal to one even gate line of the gate lines, comprising:
a third signal output unit for receiving a first even start signal and a second input signal to generate the third driving signal; and
a third shift register unit for receiving the first even start signal and a second clock signal to generate a second even start signal; and
a fourth circuit unit for outputting a fourth driving signal to another even gate line of the gate lines, the fourth circuit unit electrically coupling to the third circuit unit and comprising:
a fourth signal output unit for receiving the second even start signal and the second input signal to generate the fourth driving signal; and
a fourth shift register unit for receiving the second even start signal and the second clock signal to generate a third even start signal.
2. The gate driver of claim 1, wherein the first clock signal comprises a first positive phase clock signal and a first opposite phase clock signal, and wherein the phase of the first positive phase clock signal is opposite to the phase of the first opposite phase clock signal.
3. The gate driver of claim 2, wherein the first circuit unit is configured to receive the first positive phase clock signal, and the second circuit unit is configured to receive the first opposite phase clock signal.
4. The gate driver of claim 1, wherein the second clock signal comprises a second positive phase clock signal and a second opposite phase clock signal, and wherein the phase of the second positive phase clock signal is opposite to the phase of the second opposite phase clock signal.
5. The gate driver of claim 4, wherein the third circuit unit is configured to receive the second positive phase clock signal, and the fourth circuit unit is configured to receive the second opposite phase clock signal.
6. The gate driver of claim 1, wherein the first clock signal and the second clock signal are of the same waveform and separated from a predetermined time interval.
7. The gate driver of claim 1, wherein the first odd start signal and the first even start signal are of the same waveform and separated from a predetermined time interval.
8. The gate driver of claim 1, wherein the first input signal and the second input signal are of the same wave form, and the second input signal lags half a period behind the first input signal.
9. The gate driver of claim 8, wherein the period of the first input signal is divided into four durations, the first input signal is at a high level in the first, third, and fourth durations, and the first input signal is at a low level in the second duration.
10. The gate driver of claim 1, wherein the first signal output unit comprises:
a first transistor, the gate electrode and the first sourcedrain electrode of the first transistor receiving the first odd start signal;
a second transistor, the first sourcedrain electrode of the second transistor receiving the first input signal, the second sourcedrain electrode of the second transistor outputting the first driving signal;
a third transistor, the gate electrode of the third transistor receiving the second odd start signal, the second sourcedrain electrode of the third transistor coupling to a power voltage; and
a fourth transistor, the gate electrode of the fourth transistor receiving the second odd start signal, the second sourcedrain electrode of the fourth transistor coupling to the power voltage;
wherein the first sourcedrain electrode of the third transistor, the second sourcedrain electrode of the first transistor and the gate electrode of the second transistor are coupled with one another, and the first sourcedrain electrode of the fourth transistor couples to the second sourcedrain electrode of the second transistor, so as to stabilize the first driving signal.
11. The gate driver of claim 10, wherein the first signal output unit further comprises a first pull-down circuit, and the first pull-down circuit couples to the gate electrode and the second sourcedrain electrode of the second transistor and the power voltage so as to stabilize the first driving signal.
12. The gate driver of claim 1, wherein the first shift register unit comprises:
a fifth transistor, the gate electrode and the first sourcedrain electrode of the fifth transistor receiving the first odd start signal; and
a sixth transistor, the first sourcedrain electrode of the sixth transistor receiving the first clock signal, the second sourcedrain electrode of the sixth transistor outputting the second odd start signal, the gate electrode of the sixth transistor coupling to the second sourcedrain electrode of the fifth transistor, so as to output the second odd start signal according to the first odd start signal and the first clock signal.
13. The gate driver of claim 12, wherein the first shift register unit further comprises a second pull-down circuit, and the second pull-down circuit couples to the gate electrode and the second sourcedrain electrode of the sixth transistor and the power voltage, so as to stabilize the second odd start signal.
14. The gate driver of claim 1, wherein the third signal output unit comprises:
a seventh transistor, the gate electrode and the first sourcedrain electrode of the seventh transistor receiving the first even start signal;
an eighth transistor, the first sourcedrain electrode of the eighth transistor receiving the second input signal, the second sourcedrain electrode of the eighth transistor outputting the third driving signal;
a ninth transistor, the gate electrode of the ninth transistor receiving the second even start signal, the second sourcedrain electrode of the ninth transistor coupling to a power voltage; and
a tenth transistor, the gate electrode of the tenth transistor receiving the second even start signal, the second sourcedrain electrode of the tenth transistor coupling to the power voltage;
wherein the first sourcedrain electrode of the ninth transistor, the second sourcedrain electrode of the seventh transistor and the gate electrode of the eighth transistor are coupled with one another, and the first sourcedrain electrode of the tenth transistor couples to the second sourcedrain electrode of the eighth transistor, so as to stabilize the third driving signal.
15. The gate driver of claim 14, wherein the second signal output unit further comprises a third pull-down circuit, and the third pull-down circuit couples to the gate electrode and the second sourcedrain electrode of the eighth transistor and the power voltage so as to stabilize the third driving signal.
16. The gate driver of claim 1, wherein the second shift register unit comprises:
an eleventh transistor, the gate electrode and the first sourcedrain electrode of the eleventh transistor receiving the first even start signal; and
a twelfth transistor, the first sourcedrain electrode of the twelfth transistor receiving the second clock signal, the second sourcedrain electrode of the twelfth transistor outputting the second even start signal, the gate electrode of the twelfth transistor coupling to the second sourcedrain electrode of the eleventh transistor, so as to output the second even start signal according to the first even start signal and the second clock signal.
17. The gate driver of claim 16, wherein the second shift register unit further comprises a fourth pull-down circuit, and the fourth pull-down circuit couples to the gate electrode and the second sourcedrain electrode of the twelfth transistor and the power voltage, so as to stabilize the second even start signal.
18. A liquid crystal display, comprising:
a plurality of data lines;
a plurality of gate lines crossing the data lines to form a display cell array;
a data driver coupled to the data lines and generating a plurality of image signals to the data lines; and
a gate driver coupled to the gate lines and generating a plurality of driving signals to the gate lines, the gate driver comprising:
a plurality of first circuit units, which are electrically cascade-connected, coupled to odd gate lines of the gate lines and outputting a plurality of first driving signals to the odd gate lines, wherein each of the first circuit units comprises a first signal output unit and a first shift register unit, and the first signal output unit receives a first input signal and a first start signal to generate the first driving signal, and the first shift register unit receives the first start signal and a first clock signal to generate a next first start signal for a next first circuit unit of the first circuit units and transmits the next first start signal to the next first circuit unit; and
a plurality of second circuit units, which are electrically cascade-connected, coupled to even gate lines of the gate lines and outputting a plurality of second driving signals to the even gate lines, wherein each of the second circuit units comprises a second signal output unit and a second shift register unit, and the second signal output unit receives a second input signal and a second start signal to generate the second driving signal, and the second shift register unit receives the second start signal and a second clock signal to generate a next second start signal for a next second circuit unit of the second circuit units and transmits the next second start signal to the next second circuit unit.
19. A method for driving the liquid crystal display of claim 18, comprising:
providing a first start signal and a first input signal to the first signal output unit to generate a first driving signal, and providing a second start signal and a second input signal to the second signal output unit to generate a second driving signal; and
transmitting the first start signal and a first clock signal to the first shift register unit to generate a next first start signal for the next first circuit unit and transmitting the next first start signal to the next first circuit unit, and transmitting the second start signal and a second clock signal to the second shift register unit to generate a next second start signal for the next second circuit unit and transmitting the next second start signal to the next second circuit unit.
20. The method of claim 19, wherein the first and second clock signals are of the same waveform and separated from a predetermined time interval.
21. The method of claim 19, wherein the first and second start signals are of the same waveform and separated from a predetermined time interval.
22. The method of claim 19, wherein the first and second input signals are of the same wave form, and the second input signal lags half a period behind the first input signal.