1. A quantum cascade laser comprising:
a substrate having a first surface, a second surface opposite the first surface, and a recess provided in the second surface;
a semiconductor region provided on the first surface of the substrate;
a ridge portion extending in one direction on the semiconductor region;
a first electrode provided along the ridge portion; and
a second electrode provided on the second surface of the substrate,
wherein the semiconductor region includes a first cladding layer of a first conductivity type, a core layer, and a second cladding layer of the first conductivity type stacked in that order;
the recess is provided at a position corresponding to the ridge portion in the second surface of the substrate; and
the second electrode is provided in the recess.
2. The quantum cascade laser according to claim 1, wherein the core layer includes a plurality of active layers and a plurality of injection layers for injecting carriers into the active layers, the active layers being light-emitting regions, and
the active layers and the injection layers are alternately stacked.
3. The quantum cascade laser according to claim 1, wherein the recess includes a groove extending in the direction in which the ridge portion extends, and the groove has a bottom with a width that is substantially the same as or less than the width of the ridge portion.
4. The quantum cascade laser according to claim 3, wherein the second electrode is provided on the bottom.
5. The quantum cascade laser according to claim 1, further comprising:
an insulating layer which is provided between the second surface of the substrate and the second electrode,
wherein the insulating layer has an opening at the position of the recess, and the second electrode is directly in contact with the second surface through the opening.
6. The quantum cascade laser according to claim 5, wherein the insulating layer is composed of any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, and aluminum oxide.
7. The quantum cascade laser according to claim 1, further comprising:
a semi-insulating semiconductor layer which is provided between the second surface of the substrate and the second electrode,
wherein the semi-insulating semiconductor layer has an opening at the position of the recess, and the second electrode is directly in contact with the second surface through the opening.
8. The quantum cascade laser according to claim 7, wherein the semi-insulating semiconductor layer is doped with at least one of protons, Fe, Ti, Cr, and Co.
9. The quantum cascade laser according to claim 1, wherein the substrate has a first end facet and a second end facet,
the recess and the ridge portion each extend in the direction from the first end facet to the second end facet,
the recess has a first end and a second end, and
the first end and the second end are separated from the first end facet and the second end facet, respectively.
10. The quantum cascade laser according to claim 1, wherein the substrate further has a second recess provided in the second surface, and
the depth of the second recess is smaller than the depth of the recess.
11. The quantum cascade laser according to claim 1, wherein the first conductivity type is n-type.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A level converter, comprising:
a first latch having first and second power supply terminals, and first and second nodes;
a second latch having third and fourth power supply terminals, and third and fourth nodes;
a first transistor having a first current electrode coupled to the first node, a control electrode coupled to receive a first bias voltage, and a second current electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias voltage;
a third transistor having a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode; and
a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.
2. The level converter of claim 1, wherein the first latch comprises a pair of cross-coupled inverters.
3. The level converter of claim 1, wherein the first power supply voltage terminal is for receiving a first power supply voltage, the fourth power supply voltage terminal is coupled to ground, the second power supply voltage terminal is coupled to receive a first intermediate level voltage, and the third power supply voltage terminal is coupled to receive a second intermediate level voltage.
4. The level converter of claim 3, wherein the first and second intermediate level voltages are equal to approximately one half of the first power supply voltage.
5. The level converter of claim 1, wherein the control electrodes of the first and third transistors are coupled to the second power supply voltage terminal, and the control electrodes of the second and fourth transistors are coupled to the third power supply voltage terminal.
6. The level converter of claim 5, further comprising a digital-to-analog converter for providing a second power supply voltage to the second power supply voltage terminal, and a third power supply voltage to the third power supply voltage terminal in response to a control value.
7. The level converter of claim 6, wherein the second power supply voltage is different from the third power supply voltage.
8. The level converter of claim 1, wherein the second latch comprises:
a fifth transistor having a first current electrode coupled to the third power supply voltage terminal, a second current electrode coupled to the third node, and a control electrode;
a seventh transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode for receiving a first input signal, and a second current electrode coupled to the fourth power supply voltage terminal; and
an eighth transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the fourth power supply voltage terminal.
9. The level converter of claim 8, wherein the fifth and sixth transistors are characterized as being P-channel transistors and the seventh and eighth transistors are characterized as being N-channel transistors.
10. The level converter of claim 1, wherein the first and third transistors are characterized as being P-channel transistors and the second and fourth transistors are characterized as being N-channel transistors.
11. A level converter comprising:
a first latch having first and second power supply terminals, and first and second nodes;
a second latch having third and fourth power supply terminals, and third and fourth nodes;
a first transfer circuit having a first terminal coupled to the first node, a second terminal coupled to the third node, and a control terminal coupled to receive a first bias voltage; and
a second transfer circuit having a first terminal coupled to the second node, a second terminal coupled to the fourth node, and a control terminal coupled to receive the first bias voltage;
wherein the first power supply voltage terminal is for receiving a first power supply voltage, the second power supply voltage terminal is from receiving a first intermediate level voltage, the third power supply voltage terminal is for receiving a second intermediate level voltage, and the fourth power supply voltage terminal is coupled to ground, and wherein the first and second intermediate level voltages are between the first power supply voltage and ground.
12. The level converter of claim 11, wherein the control terminal of the first and second transfer circuits is coupled to the second power supply voltage terminal.
13. The level converter of claim 11, wherein the first transfer circuit comprises:
a first transistor having a first current electrode coupled to the first node, a control electrode for receiving the first bias voltage, and a second current electrode; and
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a second bias voltage, and a second current electrode coupled to the third node.
14. The level converter of claim 13, wherein the second transfer circuit comprises:
a third transistor having a first current electrode coupled to the second node, a control electrode for receiving the first bias voltage, and a second current electrode; and
a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode for receiving the second bias voltage, and a second current electrode coupled to the fourth node.
15. The level converter of claim 11, wherein the first latch comprises:
a first inverter having an input terminal coupled to the first node, and an output coupled to the second node; and
a second inverter having an input terminal coupled to the second node, and an output terminal coupled to the first node.
16. The level converter of claim 11, wherein the second latch comprises:
a first transistor having a first current electrode coupled to the third power supply voltage terminal, a second current electrode coupled to the third node, and a control electrode;
a second transistor having a first current electrode coupled to the third power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the control electrode of the first transistor at the fourth node;
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a first input signal, and a second current electrode coupled to the fourth power supply voltage terminal; and
a fourth transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the fourth power supply voltage terminal.
17. The level converter of claim 11, wherein the first bias voltage is provided by a digital-to-analog converter in response to receiving a control value.
18. A method for converting a signal from one voltage level to another voltage level comprising:
providing a first latch having first and second power supply voltage terminals:
providing a second latch having third and fourth power supply voltage terminals;
coupling the first latch to a second latch;
providing a first power supply voltage to the first power supply voltage terminal, and coupling the fourth power supply voltage terminal to a reference potential;
providing a first intermediate voltage to the second power supply voltage terminal, and a second intermediate voltage to the third power supply voltage terminal, wherein the first and second intermediate voltages are between the first power supply voltage and the reference potential;
providing the signal to the second latch; and
receiving a level converted signal corresponding to the signal from an output of the first latch;
wherein coupling the first latch to the second latch comprises providing first and second transistors coupled in series between a node of the first latch and a node of the second latch, the first transistor having a control electrode for receiving a first bias voltage and the second transistor having a control electrode for receiving a second bias voltage.
19. The method of claim 18, wherein the first bias voltage and the second bias voltage are provided by a digital-to-analog converter in response to a control value.