1. A digital-to-analog converter for converting a digital input into an analog output, coupled to a first voltage source and comprising:
a load circuit for rendering the analog output;
a switch circuit coupled to the load circuit and including at least one transistor for selectively conducting a current flow to the load circuit; and
a voltage booster coupled to the at least one transistor, and providing a first gate-source voltage and a second gate-source voltage to generate a voltage of a first level according to the first voltage source and the first gate-source voltage, and to generate a voltage of a second level according to the voltage of the first level and the second gate-source voltage, thereby controlling the at least one transistor to be switched on so as to conduct the current flow to the load circuit in response to the voltage of the first level or the second level;
wherein the first level and the second level vary with the first voltage source.
2. The digital-to-analog converter according to claim 1 wherein the voltage booster includes:
a current replica circuit including a first transistor; and
a switch replica circuit including a second transistor;
wherein the first gate-source voltage is provided according to a voltage at a node between a gate and a source of the first transistor, and the second gate-source voltage is provided according to a voltage at a node between a gate and a source of the second transistor; and
wherein the at least one transistor of the switch circuit is compatible with the second transistor for selectively conducting the current flow to the load circuit according to the voltage of the first level or the second level.
3. The digital-to-analog converter according to claim 2 wherein the voltage booster further includes a connection circuit coupling the voltage of the first level to the source or drain of the second transistor so as to provide the voltage of the first level and the voltage of the second level from the source and drain of the second transistor.
4. The digital-to-analog converter according to claim 3 wherein the connection circuit is a wiring between the gate of the first transistor and the source of the second transistor.
5. The digital-to-analog converter according to claim 3 wherein the connection circuit includes an operational amplifier which functions as virtual short circuit to couple the gate of the first transistor to the source of the second transistor.
6. The digital-to-analog converter according to claim 3 wherein the connection circuit includes a source follower including a third transistor compatible to the second transistor for providing a third gate-source voltage, wherein a voltage difference between the voltage of the first level and the third gate-source voltage is coupled to the drain of the second transistor.
7. The digital-to-analog converter according to claim 2 wherein the gate and drain of the second transistor are coupled to each other and the source of the first transistor is coupled to the first voltage source.
8. The digital-to-analog converter according to claim 2 further comprising:
a current source for providing a reference current, coupled to the switch circuit and including at least one transistor compatible with the first transistor for guiding the reference current to form the current flow to the load circuit.
9. The digital-to-analog converter according to claim 1 wherein the first level is substantially equal to a voltage difference between the first voltage source and the first gate-source voltage, and the second level is substantially equal to a voltage difference between the first voltage source and the second gate-source voltage.
10. A voltage booster of a digital-to-analog converter, comprising:
a first transistor having at least two electrodes and providing a first voltage between electrodes; and
a second transistor having at least two electrodes and providing a second voltage between electrodes;
wherein a voltage of a first level is generated according to a first voltage source and the first voltage between electrodes, a voltage of a second level is generated according to the first level and the second voltage between electrodes, and the voltage of the first level or the second level is selectively provided for the digital-to-analog converter to generate an analog output according to a digital input.
11. The voltage booster according to claim 10 wherein one of the two electrodes of the first transistor is coupled to the first voltage source so that a reference level is provided from the other of the two electrodes of the first transistor to provide the voltage of the first level, and one of the two electrodes of the second transistor is coupled to the reference level so that the voltage of the first level and the voltage of the second level are provided from the two electrodes of the second transistor, respectively.
12. The voltage booster according to claim 11, wherein the voltage of the first level or the second level is selectively provided to a current-guiding circuit of the digital-to-analog converter, which includes:
a current source for providing a reference current, including at least one transistor compatible with the first transistor for guiding the reference current;
a load circuit for rendering the analog output; and
a switch circuit coupled between the current source and the load circuit and including at least one transistor compatible with the second transistor for optionally conducting the flow of the reference current to the load circuit according to the voltage of the first level or the second level.
13. The voltage booster according to claim 11, further comprising a connection circuit coupling one of the two electrodes of the second transistor to the reference level.
14. The voltage booster according to claim 13 wherein the connection circuit is a wiring for connecting the first transistor and the second transistor so as to have the reference level directly coupled to the one of the two electrodes of the second transistor.
15. The voltage booster according to claim 13 wherein the connection circuit includes an operational amplifier which functions as virtual short circuit to couple the reference level provided by the first transistor to the one of the two electrodes of the second transistor.
16. The voltage booster according to claim 13 wherein the connection circuit includes a source follower including a third transistor which has at least two electrodes and provides a voltage between electrodes, wherein a voltage difference between the reference level and the third voltage between electrodes is coupled to the one of the two electrodes of the second transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for acquiring medical images, comprising:
applying, during a first period, a plurality of radio frequency (RF) pulses o an area of interest, wherein the RF pulses applied during the first period are Kaiser-Bessel pulses;
applying, during a second period, a plurality of 180 degree RF preparation pulses to the area;
applying, during a third period, a plurality of 180 degree RF pulses to the area to acquire a center of a k-space;
applying, during a fourth period, a plurality of RF pulses to the area, wherein the RF pulses applied during the fourth period have an angle smaller than the 180 degree RF pulses applied during the third period;
applying, during a fifth period, a plurality of constant RF pulses to the area to acquire outer lines of the k-space, wherein the RF pulses applied during the fifth period have an angle less than the angle of the RF pulses applied during the fourth period; and
generating an image of the area by using a steady-state free precession echo readout.
2. The method of claim 1, wherein the image is a magnetic resonance image.
3. The method of claim 1, wherein the RF pulses of the first to fifth periods are generated by controlling an RF coil array adapted to produce a plurality of magnetic fields in the area.
4. The method of claim 1, wherein the area of interest includes an anatomical part of a human.
5. The method of claim 1, wherein the image is T2 weighted.
6. The method of claim 1, wherein the steady-state free precession echo readout begins after the second period.
7. A method for acquiring medical images, comprising:
applying, during a first period, a plurality of radio frequency (RF) pulses to an area of interest, wherein the RF pulses applied during the first period are Kaiser-Bessel pulses;
applying, during a second period, a plurality of 180 degree RF pulses to the area to acquire a center of a k-space;
applying, during a third period, a plurality of RF pulses to the area, wherein the RF pulses applied during the third period have an angle smaller than the 180 degree RF pulses applied during the second period;
applying, during a fourth period, a plurality of constant RF pulses to the area to acquire outer lines of the k-space, wherein the RF pulses applied during the fourth period have an angle less than the angle of the RF pulses applied during the third period; and
generating an image of the area by using a steady-state free precession echo readout.
8. The method of claim 7, wherein the image is a magnetic resonance image.
9. The method of claim 7, wherein the RF pulses of the first to fourth periods are generated by controlling an RF coil array adapted to produce a plurality of magnetic fields in the area.
10. The method of claim 7, wherein the area of interest includes an anatomical part of a human.
11. The method of claim 7, wherein the image is T2 weighted.
12. The method of claim 7, wherein the steady-state free precession echo readout begins after the first period.
13. A method for acquiring medical images, comprising:
applying, during a first period, a plurality of radio frequency (RF) pulses to an area of interest, wherein the RF pulses applied during the first period are linear ramp type pulses;
applying, during a second period, a plurality of 180 degree RF pulses to the area to acquire a center of a k-space;
applying, during a third period, a plurality of RF pulses to the area, wherein the RF pulses applied during the third period have an angle smaller than the 180 degree RF pulses applied during the second period;
applying, during a fourth period, a plurality of constant RF pulses to the area to acquire outer lines of the k-space, wherein the RF pulses applied during the fourth period have an angle less than the angle of the RF pulses applied during the third period; and
generating an image of the area by using a steady-state free precession echo readout.
14. The method of claim 13, wherein the image is a magnetic resonance image.
15. The method of claim 13, wherein the RF pulses of the first to fourth periods are generated by controlling an RF coil array adapted to produce a plurality of magnetic fields in the area.
16. The method of claim 13, wherein the area of interest includes an anatomical part of a human.
17. The method of claim 13, wherein the image is T2 weighted.
18. The method of claim 13, wherein the steady-state free precession echo readout begins after the first period.
19. A method for acquiring medical images, comprising:
applying, during a first period, a plurality of radio frequency (RF) pulses to an area of interest, wherein the RF pulses applied during the first period are Kaiser-Bessel pulses;
applying, during a second period, a plurality of RF pulses to the area, wherein the RF pulses applied during the second period have an angle greater than an angle of the Kaiser-Bessel pulses applied during the first period;
applying, during a third period, a plurality of RF pulses to the area, wherein the RF pulses applied during the third period ramp up the angle of the RF pulses applied during the second period to about 180 degrees;
applying, during a fourth period, a plurality of 180 degree RF pulses to the area to acquire a center of a k-space;
applying, during a fifth period, a plurality of RF pulses to the area, wherein the RF pulses applied during the fifth period have an angle smaller than the 180 degree RF pulses applied during the fourth period;
applying, during a sixth period, a plurality of constant RF pulses to the area to acquire outer lines of the k-space, wherein the RF pulses applied during the sixth period have an angle less than the angle of the RF pulses applied during the fifth period; and
generating an image of the area by using a steady-state free precession echo readout.
20. The method of claim 19, wherein the steady-state free precession echo readout begins after the second period.