1. An electric component arrangement, comprising a semiconductor component and a varistor body, which is contact-connected to the semiconductor component in order to protect the latter against electrostatic discharges, wherein the semiconductor component and the varistor body are arranged on a common carrier containing a highly thermally conductive ceramic.
2. The component arrangement as claimed in claim 1, wherein the highly thermally conductive ceramic of the carrier comprises at least one of the materials aluminum nitride, gallium nitride, silicon carbide, hafnium oxide, manganese oxide.
3. The component arrangement as claimed in claim 1, wherein the carrier contains the highly thermally conductive ceramic as matrix and a metal as filler.
4. The component arrangement as claimed in claim 1, wherein the carrier is embodied as a plate.
5. The component arrangement as claimed in claim 1, wherein the carrier has conductor tracks that are electrically decoupled from one another.
6. The component arrangement claim 5, wherein the semiconductor component and the varistor body are contact-connected to the conductor tracks.
7. The component arrangement as claimed in claim 5, wherein the varistor body has external electrical contacts on its side facing the carrier, which make contact with at least one conductor track.
8. The component arrangement as claimed in claim 1, wherein the varistor body is connected in parallel with the semiconductor component.
9. The component arrangement as claimed in claim 1, wherein the varistor body has at least one internal electrode.
10. The component arrangement as claimed in claim 1, wherein the varistor body has at least one external electrical contact and also at least one internal electrode, wherein the internal electrode is connected to the external contact by means of at least one plated through-hole.
11. The component arrangement as claimed in claim 1, wherein the varistor body contains a composite material composed at least of a varistor ceramic as matrix and a highly theiinally conductive material as filler.
12. The component arrangement as claimed in claim 1, wherein the carrier with the semiconductor component mounted on it and the varistor body is integrated in a housing, wherein the housing has a thermally conductive region which is connected to the carrier and which is thermally coupled to the carrier.
13. The component arrangement as claimed in claim 1, wherein the varistor body comprises a monolithic multilayer varistor.
14. The component arrangement as claimed in claim 1, wherein the semiconductor component is chosen from the components: optoelectronic component, LED, capacitor, multilayer capacitor, thermistor, multilayer thermistor, diode, amplifier.
15. The component arrangement as claimed in claim 1, additionally comprising a thermistor which contributes, in a manner dependent on its resistancetemperature characteristic curve, to the regulation of the control current of the semiconductor component.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A faulty address control circuit comprising:
a variable resistance fuse unit configured to be driven in response to an address signal, a resistance value of the variable resistance fuse unit being determined based on an amount of an applied current to the variable resistance fuse unit;
a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and
an address storage and determination unit configured to receive the address signal, and be driven by the driving signal to output the address signal or an inverted signal of the address signal.
2. The faulty address control circuit according to claim 1, wherein the variable resistance fuse unit comprises a variable resistance element in which a state of crystals is changed based on the amount of applied current.
3. The faulty address control circuit according to claim 1, wherein the variable resistance fuse unit comprises:
a first switching element connected between a current supply terminal and a first node and driven in response to the address signal; and
a variable resistance element connected between the first node and a ground voltage terminal, wherein a resistance value of the variable resistance element represents the resistance value of the variable resistance fuse unit, and the resistance value of the variable resistance element is determined based on an amount of a current applied through the first switching element.
4. The faulty address control circuit according to claim 3, wherein the variable resistance element comprises an element whose state of crystals is changed based on the amount of the applied current.
5. The faulty address control circuit according to claim 4, wherein the variable resistance element comprises a phase change material.
6. The faulty address control circuit according to claim 4, wherein the variable resistance element comprises a germaniumstibiumtellurium (Ge2Sb2Te5: GST) compound.
7. The faulty address control circuit according to claim 3, wherein the driving unit comprises:
a current source connected to a power supply voltage terminal;
a second switching element connected between the current source and a second node and driven in response to the faulty address control signal; and
a third switching element connected between the second node and the first node and driven in response to the faulty address control signal.
8. The faulty address control circuit according to claim 7, wherein the address storage and determination unit comprises:
a latch section configured to latch an output signal of the second node;
a first transmission gate configured to be driven in response to an output signal of the latch section to output the inverted signal of the address signal; and
a second transmission gate configured to be driven in response to the output signal of the latch section to output a non-inverted signal of the address signal.
9. The faulty address control circuit according to claim 8, wherein the address storage and determination unit outputs the inverted signal of the address signal through the first transmission gate when the variable resistance element is in a high resistance state.
10. The faulty address control circuit according to claim 8, wherein the address storage and determination unit outputs the non-inverted signal of the address signal through the second transmission gate when the variable resistance element is in a low resistance state.
11. A semiconductor memory apparatus comprising:
a main cell array;
a redundancy cell array;
an address buffer configured to convert an external address signal into an internal address signal to output the internal address signal;
a faulty address control circuit configured to store an address of a faulty memory cell in the main cell array by changing a resistance value based on an amount of an applied current, compare the internal address signal with the address of the faulty memory cell as the internal address signal is inputted to output a decoding enable signal;
a main decoder configured to be driven in response to the decoding enable signal to generate a signal to access a memory cell in the main cell array; and
a redundancy decoder configured to be driven in response to the decoding enable signal to generate a signal to access a memory cell in the redundancy cell array.
12. The semiconductor memory apparatus according to claim 11, wherein the faulty address control circuit comprises:
a variable resistance fuse unit configured to be driven in response to the internal address signal, a resistance value of the variable resistance fuse unit being determined based on the amount of the applied current;
a driving unit configured to output a driving signal based on the resistance value of the variable resistance fuse unit in response to a faulty address control signal; and
an address storage and determination unit configured to receive the internal address signal, and is driven by the driving signal to output the internal address signal or an inverted signal of the internal address signal.
13. The semiconductor memory apparatus according to claim 12, wherein the variable resistance fuse unit comprises a variable resistance element in which a state of crystals is changed based on the amount of the applied current.
14. The semiconductor memory apparatus according to claim 12, wherein the variable resistance fuse unit comprises:
a first switching element connected between a current supply terminal and a first node and driven in response to the internal address signal; and
a variable resistance element connected between the first node and a ground voltage terminal, a resistance value of the variable resistance element being determined based on an amount of a current applied through the first switching element.
15. The semiconductor memory apparatus according to claim 14, wherein the variable resistance element comprises an element in which a state of crystals is changed based on the amount of the applied current.
16. The semiconductor memory apparatus according to claim 15, wherein the variable resistance element comprises a phase change material.
17. The semiconductor memory apparatus according to claim 15, wherein the variable resistance element comprises a germaniumstibiumtellurium (Ge2Sb2Te5: GST) compound.
18. The semiconductor memory apparatus according to claim 14, wherein the driving unit comprises:
a current source connected to a power supply voltage terminal;
a second switching element connected between the current source and a second node and driven in response to the faulty address control signal; and
a third switching element connected between the second node and the first node and driven in response to the faulty address control signal.
19. The semiconductor memory apparatus according to claim 18, wherein the address storage and determination unit comprises:
a latch section configured to latch an output signal of the second node;
a first transmission gate configured to be driven in response to an output signal of the latch section to output the inverted signal of the internal address signal; and
a second transmission gate configured to be driven in response to the output signal of the latch section to output a non-inverted signal of the internal address signal.
20. The semiconductor memory apparatus according to claim 19, wherein the address storage and determination unit outputs the inverted signal of the internal address signal through the first transmission gate when the variable resistance element is in a high resistance state.
21. The semiconductor memory apparatus according to claim 19, wherein the address storage and determination unit outputs the non-inverted signal of the internal address signal through the second transmission gate when the variable resistance element is in a low resistance state.
22. A faulty address control method using one or more variable resistance elements which are determined in resistance values based on an amount of an applied current, the method comprising the steps of:
inputting a faulty address signal; and
applying a programming current to a variable resistance element selected by the faulty address signal and determining a resistance value of the variable resistance element.
23. The faulty address control method according to claim 22, wherein the step of determining the resistance value of the variable resistance element comprises the step of:
controlling the variable resistance element to which a fault bit of the faulty address signal is applied, to a low resistance state.
24. The faulty address control method according to claim 22, further comprising the step of:
comparing an access address signal with the faulty address signal in response to the access address signal for accessing a main memory cell.
25. The faulty address control method according to claim 24, further comprising the step of:
driving a main decoder when the access address signal and the faulty address signal do not match each other.
26. The faulty address control method according to claim 24, further comprising the step of:
driving a redundancy decoder when the access address signal and the faulty address signal match each other.
27. A faulty address control method using one or more variable resistance elements, resistance values of the one or more variable resistance elements being determined based on an amount of an applied current, the method comprising the steps of:
inputting an uppermost fault bit of a faulty address signal to a high level;
applying a programming current to a variable resistance element selected by the fault bit and determining a resistance value of the variable resistance element; and
repeating the above-described process for each fault bit of the faulty address signal and storing a faulty address.
28. The faulty address control method according to claim 27, further comprising the step of:
comparing an access address signal with the faulty address in response to the access address signal for accessing a main memory cell.