1-59. (canceled)
60. A multi-chip packaged integrated circuit part to mount to a printed circuit board of a memory module, the multi-chip packaged integrated circuit part comprising:
an integrated circuit package including
a slave memory controller (SMC) die, and
one or more pairs of
a spacer under the slave memory controller die, and
a flash memory die under the spacer,
wherein the flash memory die is larger than the spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.
61. The multi-chip packaged integrated circuit part of claim 60, wherein the integrated circuit package is a multi-chip module integrated circuit package.
62. The multi-chip packaged integrated circuit part of claim 60, further comprising:
a first plurality of conductors to electrically coupled the slave memory controller die to one or more independent pads of a pin-out of the integrated circuit package;
a second plurality of conductors to electrically couple the slave memory controller die to one or more joint pads of the pin-out; and
a third plurality of conductors to electrically couple one or more of the flash memory die to the one or more joint pads of the pin-out to electrically couple the flash memory die to the slave memory control die.
63. The multi-chip packaged integrated circuit part of claim 60, wherein
each of the spacers is a dielectric or insulator so active portions of the circuitry of the flash memory die do not short to active portions of a neighboring integrated circuit die.
64. The multi-chip packaged integrated circuit part of claim 60, wherein
the slave memory controller die includes a processor.
65. The multi-chip packaged integrated circuit part of claim 64, wherein
the slave memory controller die further includes a scratch pad memory coupled to the processor.
66. The multi-chip packaged integrated circuit part of claim 60, wherein
under the slave memory controller die and over the one or more pairs of the spacer and the flash memory die, the multi-chip packaged integrated circuit part further includes
a first spacer;
a processor under the first spacer;
a second spacer under the processor; and
a scratch pad memory die under the second spacer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A dielectric ceramic comprising an oxide of the following composition formula:
\u03b1BaO.\u03b2Nd2O3.\u03b3TiO2
wherein 14\u2266\u03b1\u226621, 4\u2266\u03b2\u226621, 65\u2266\u03b3\u226675, and \u03b1+\u03b2+\u03b3=100 and
containing not less than 3 mass % nor more than 9 mass % of yttrium in terms of Y2O3, 0.5 mass % or less (except for 0 mass %) of manganese in terms of MnCO3, and not less than 0.25 mass % nor more than 1 mass % of aluminum in terms of Al2O3.
2. The dielectric ceramic according to claim 1, wherein the values of \u03b1, \u03b2 and \u03b3 are 15\u2266\u03b1\u226619, 14\u2266\u03b2\u226621, and 68\u2266\u03b3\u226672, respectively.
3. (canceled)
4. The dielectric ceramic according to claim 1, comprising a crystal of Ba4.5Nd9Ti18O54.
5. The dielectric ceramic according to claim 4, wherein lattice constants a, b, and c of the crystal, which are calculated from an X-ray diffraction chart by Rietveld method, satisfy the following inequalities.
22.29\u2266a\u226622.32;
7.66\u2266b\u22667.69; and
12.14\u2266c\u226612.17
6. The dielectric ceramic according to claim 5, wherein in the X-ray diffraction chart, a value of IAIC is 0.04 or less where IA represents maximum peak strength of Ba1.23Al2.46Ti5.5O16 crystal of 2\u03b8=28.1-28.3\xb0 and Ic represents maximum peak strength of Ba4.5Nd9Ti18O54 crystals of 2\u03b8=31.5-31.7\xb0.
7. The dielectric ceramic according to claim 1, wherein the void ratio is 4% or less.
8. A resonator using the dielectric ceramic according to claim 1 as a dielectric material.