1. A method comprising:
transmitting a frame having status information and non-status information between a device and a host controller;
storing the status information of the frame in a buffer;
updating the non-status information in a non-status register;
after updating the non-status information in the non-status register, determining if the frame has an error; and
updating a status register of the host controller if the frame includes no error.
2. The method of claim 1 wherein determining if the frame has an error includes transmitting a cyclic redundancy code (CRC) applied to the frame being transmitted.
3. The method of claim 1 further comprising transmitting a next set of data transfer commands after updating the status register of the host controller.
4. The method of claim 3 wherein the transmitting of the frame and the transmitting of the next set of data transfer commands is performed in a serial fashion.
5. The method of claim 3 wherein the data transfer commands are selected from a group of interface specifications consisting of Advanced Technology Attachment (ATA) specification, Serial ATA specification, and Advanced Technology Attachment Packet Interface (ATAPI) specification.
6. The method of claim 1 further comprising establishing shadow task file registers within the host controller.
7. The method of claim 6 wherein the shadow task file registers include the status registers and non-status registers.
8. The method of claim 6 wherein the shadow task file registers emulate legacy parallel task file configurations.
9. The method of claim 1 wherein the transmitting of the frame from the device to the host controller includes transmitting a register frame information structure (FIS).
10. The method of claim 1 wherein the transmitting of the frame from the device to the host includes transmitting a programmed inputoutput setup frame information structure (PIO SETUP FIS).
11. The method of claim 1 wherein the updating of the non-status information in the plurality of non-status registers occurs irrespective of whether or not a cyclic redundancy code (CRC) of the frame has been verified.
12. A system comprising:
a host controller;
a device connected to the host controller via a data transmission channel, the data transmission channel configured to transmit a frame having status information and non-status information between the device and the host controller;
a status register in the host controller, the status register being configured to be updated if the frame has no errors;
a buffer for storing the status information of the frame; and
a non-status register in the host controller, the non-status register configured to be updated with the non-status information of the frame before the status register is updated with the status information stored in the buffer.
13. The system of claim 12 wherein the frame includes a cyclic redundancy code (CRC) configured to check for errors in the frame.
14. The system of claim 12 further comprising connections configured to transmit a next set of data transfer commands after the status registers have been updated.
15. The system of claim 14 wherein the connection is serial.
16. The system of claim 14 wherein the next set of data transfer commands are selected from a group of interface specifications consisting of Advanced Technology Attachment (ATA) specification, Serial ATA specification, and Advanced Technology Attachment Packet Interface (ATAPI) specification.
17. The system of claim 12 wherein the frame is a register frame information structure (FIS).
18. The system of claim 12 wherein the frame is a programmed inputoutput setup frame information structure (PIO SETUP FIS).
19. The system of claim 12 wherein the non-status register in the host controller is updated irrespective of whether or not a cyclic redundancy code (CRC) of the frame has been verified.
20. A computer program product residing on a computer readable media comprises instructions for causing a processor to:
transmit a frame having status information and non-status information between the device and the host controller;
store the status information of the frame in a buffer;
update the non-status information in a non-status register;
after the update of the non-status information in the non-status register, determine if the frame has an error; and
update a status register of the host controller if the frame includes no error.
21. The computer program product of claim 20 further comprising instructions for causing the processor to transmit a cyclic redundancy code (CRC) applied to the frame being transmitted.
22. The computer program product of claim 20 further comprising instructions for causing the processor to transmit a next set of data transfer commands after the processor has updated the status register of the host controller.
23. The computer program product of claim 20 wherein the instructions causing the processor to transmit the frame and transmit the next set of data transfer commands is performed in a serial fashion.
24. The computer program product of claim 22 wherein the data transfer commands are selected from a group of interface specifications consisting of Advanced Technology Attachment (ATA) specification, Serial ATA specification, and Advanced Technology Attachment Packet Interface (ATAPI) specification.
25. The computer program product of claim 20 further comprising instructions for causing the processor to establish a plurality of shadow task file registers within the host controller, the plurality of shadow task file registers including the status registers and non-status registers.
26. The computer program product of claim 25 wherein the plurality of shadow task file registers emulate legacy parallel task file configurations.
27. The computer program product of claim 20 wherein the frame is a register frame information structure (FIS).
28. The computer program product of claim 20 wherein the frame is a programmed inputoutput setup frame information structure (PIO SETUP FIS).
29. The computer program product of claim 20 wherein the instructions causing the processor to update the non-status information in the non-status register occurs irrespective of whether or not a cyclic redundancy code (CRC) of the frame has been verified.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
an antenna port;
a tuning block coupled to the antenna port, the tuning block having a plurality of discrete elements, wherein a first one of the discrete elements has a first weight and a second one of the discrete elements has a second weight different from the first weight; and
a tuning circuit configured to:
detect a first transferred power when operating the tuning block with the first element but not the second element coupled to the antenna port;
detect a second transferred power when operating the tuning block with at least the second element coupled to the antenna port;
compare the first and second transferred powers; and
based on the comparison, couple at least one of the first and second elements to the antenna port for subsequent IC operations.
2. The IC of claim 1, wherein the plurality of discrete elements are capacitors.
3. The IC of claim 1, wherein the tuning circuit is further configured to:
sequentially increment or decrement through a plurality of impedance settings by coupling the plurality of discrete elements to the antenna port;
determine a maximum transferred power; and
store an impedance setting associated with the maximum transferred power.
4. The IC of claim 3, wherein the tuning circuit is further configured to:
roll over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting, respectively;
continue sequentially incrementing or decrementing upon rolling over to the minimum impedance setting or the maximum impedance setting, respectively; and
stop incrementing or decrementing when the impedance setting is equal to the stored impedance setting.
5. The IC of claim 3, wherein the tuning circuit is further configured to:
start the sequence based on a default impedance setting or a value in a randomizing register upon powering up; and
roll over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting, respectively.
6. The IC of claim 5, wherein the tuning circuit is configured to detect the second transferred power when operating the tuning block with the first element and the second element coupled to the antenna port.
7. The IC of claim 1, wherein the tuning circuit is configured to detect the first transferred power by measuring a voltage.
8. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:
an antenna port;
a tuning block coupled to the antenna port, the tuning block having a first discrete element having a first weight and a second discrete element having a second weight different from the first weight; and
a tuning circuit configured to:
couple the first element but not the second element to the antenna port;
subsequently couple at least the second element to the antenna port; and
then couple at least one of the first and second elements to the antenna port to maximize transferred power for subsequent IC operations.
9. The IC of claim 8, wherein the first and second discrete elements are capacitors.
10. The IC of claim 8, wherein the tuning circuit is further configured to:
sequentially increment or decrement through a plurality of impedance settings by coupling at least one of the first and second elements to the antenna port;
determine a maximum transferred power; and
store an impedance setting associated with the maximum transferred power.
11. The IC of claim 10, wherein the tuning circuit is further configured to:
roll over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting, respectively;
continue sequentially incrementing or decrementing upon rolling over to the minimum impedance setting or the maximum impedance setting, respectively; and
stop incrementing or decrementing when the impedance setting is equal to the stored impedance setting.
12. The IC of claim 10, wherein the tuning circuit is further configured to:
start the sequence based on a default impedance setting or a value in a randomizing register; and
roll over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting, respectively.
13. The IC of claim 8, wherein the tuning circuit is configured to subsequently couple the first and second elements to the antenna port before maximizing transferred power for subsequent IC operations.
14. A method to adjust power transfer in a Radio Frequency Identification (RFID) integrated circuit (IC), the method comprising:
detecting a first transferred power when coupling a first element but not a second element to an antenna port of the IC, wherein the first element has a first weight and the second element has a second weight different from the first;
detecting a second transferred power when coupling at least the second element to the antenna port;
comparing the first and second transferred powers; and
based on the comparison, coupling at least one of the first and second elements to the antenna port for subsequent IC operation.
15. The method of claim 14, wherein the first element and the second element are capacitors.
16. The method of claim 14, further comprising:
sequentially incrementing or decrementing through a plurality of impedance settings by coupling at least one of the first element and the second element to the antenna port;
determining a maximum transferred power from the antenna; and
storing an impedance setting associated with the maximum transferred power.
17. The method of claim 16, further comprising:
rolling over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting, respectively;
continuing sequentially incrementing or decrementing upon rolling over to the minimum impedance setting or the maximum impedance setting, respectively; and
stopping incrementing or decrementing when the impedance setting is equal to the stored impedance setting.
18. The method of claim 16, further comprising:
starting the sequence based on a default impedance setting or a value in a randomizing register; and
rolling over to a minimum impedance setting or a maximum impedance setting subsequent to incrementing to the maximum impedance setting or decrementing to the minimum impedance setting.
19. The method of claim 14, further comprising:
detecting the second transferred power when coupling the first element and the second element to the antenna port.
20. The method of claim 14, further comprising detecting the first transferred power by measuring a voltage.