1. A display device comprises:
a plurality of pixels formed on a substrate; and
a driver circuit that drives the plurality of pixels, wherein the driver circuit includes a shift register circuit, the shift register circuit includes a first basic circuit, a second basic circuit, and a third basic circuit that are connected in tandem at multi stages, and each of the first, second, and third basic circuits includes:
a first transistor of a second conductivity type having a control electrode to which a second supply voltage is applied;
a second transistor of the second conductivity type having a first electrode connected to a second electrode of the first transistor and a second electrode connected to an output node;
a third transistor of a first conductivity type having a first electrode to which a first supply voltage is applied and a second electrode connected to the output node directly or through another transistor, the first conductivity type being different from the second conductivity type; and
a fourth transistor of the first conductivity type having a first electrode to which the first supply voltage is applied and a second electrode connected to the second electrode of the third transistor,
a clock signal is supplied to a first electrode of the first transistor, a set signal is supplied to a control electrode of the second transistor, a reset signal is supplied to a control electrode of the fourth transistor, and a voltage of the output node is an output of a scanning circuit, and
wherein a common clear signal is supplied to respective control electrode of the third transistor of each of the first, second, and third basic circuits, a first clock is supplied to a respective first electrode of the first transistor of each of the first and third basic circuits, a second clock that is different in phase from the first clock is supplied to a first electrode of the first transistor of the second basic circuit, an output of the first basic circuit is supplied as the set signal to a control electrode of the second transistor of the second basic circuit, an output of the second basic circuit is supplied as the set signal to a control electrode of the second transistor of the third basic circuit, and an inversion output of the third basic circuit is supplied to a control electrode of the fourth transistor of the first basic, circuit, and
wherein each of the first, second, third, and fourth transistors of each of the first, second, and third basic circuits comprises a semiconductor layer made of polysilicon formed on the substrate.
2. The display device according to claim 1; wherein each of the first; second, and third basic circuits further comprises a fifth transistor of the first conductivity type having a first electrode to which the first supply voltage is applied and a second electrode connected to the second electrode of the third transistor, and a voltage resulting from inverting the voltage of the output node is applied to a control electrode of the fifth transistor of each of the first. second, and third basic circuits . . . .
3. The display device according to claim 1, wherein each of the first, second, and third basic circuits further comprises a sixth transistor of the first conductivity type having a first electrode connected to the second electrode of the third transistor and a second electrode connected to the output node, and wherein a control electrode of the sixth transistor of each of the first, second, and third basic circuits is connected to the control electrode of the second transistor, the set signal is supplied to the control electrode of the sixth transistor of each of the first, second, and third basic circuits, and the second electrode of the third transistor of each of the first, second, and third basic circuits is connected to the output node through the sixth transistor.
4. The display device according to claim 1,
wherein each of the first, second, and third basic circuits further comprises a buffer circuit that is connected to the output node, and
the output of the buffer circuit is the output of the scanning circuit.
5. The display device according to claim 4,
wherein the buffer circuit of each of the first, second, and third basic circuit includes inverters that are connected in tandem.
6. The display device according to claim 1,
for each of the first, second, and third basic circuits, when Vck is an amplitude of the clock signal, and Vh is an amplitude of the voltage of the output node, Vck<Vh is satisfied.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of estimating motion, the method comprising:
performing one or more refinement searches, wherein each of the one or more refinement searches comprises, on each of a plurality of macroblocks of the current frame:
identifying one or more candidates in a reference frame;
reducing the one or more candidates;
loading the reduced candidates from a storage element; and
measuring one or more distortion values based, at least in part, on the reduced candidates; and
encoding motion data based, at least in part, on the one or more refinement searches.
2. The method of claim 1 wherein reducing the one or more candidates comprises reducing the one or more candidates such that the number of reduced candidates does not exceed a load-balancing constraint.
3. The method of claim 2 wherein the load-balancing constraint is based, at least in part, on a complexity of a macroblock, to which the first plurality of candidates belongs.
4. The method of claim 1 wherein reducing the one or more candidates comprises reducing the one or more candidates based, at least in part, on a relative proximity of each of the candidates.
5. The method of claim 4 wherein reducing the one or more candidates further comprises merging two or more candidates into a single candidate.
6. The method of claim 1 wherein the storage element comprises a dynamic random access memory (DRAM).
7. The method of claim 1 wherein loading the reduced candidates comprises:
storing the reduced candidates to an on-chip memory; and
loading the reduced candidates from the on-chip memory.
8. The method of claim 1 wherein measuring one or more distortion values comprises measuring one or more distortion values in a search area around each of the reduced candidates
9. The method of claim 1 wherein measuring one or more distortion values comprises measuring one or more distortion values for each candidate according to one or more block shapes.
10. The method of claim 9 wherein measuring one or more distortion values further comprises:
measuring distortion values for a first block shape; and
calculating distortion values for the one or more block shapes based, at least in part, on a summation of the measured distortion values for the first block shape.
11. The method of claim 9 further comprising storing a best candidate for each of the block shapes.
12. The method of claim 1 wherein identifying one or more candidates in a reference frame comprises identifying one or more candidates based, at least in part, on a previous refinement search.
13. The method of claim 12 wherein identifying one or more candidates comprises identifying one or more candidates based, at least in part, on a voting scheme.
14. The method of claim 13 wherein the voting scheme comprises:
assigning a vote to each of a plurality of best candidates based, at least in part, on one or more best candidates from the previous refinement search; and
resolving tie-breakers based, at least in part, on a respective block size of each of the plurality of best candidates.
15. The method of claim 1 wherein encoding motion data comprises determining a partitioning for a macroblock.
16. The method of claim 15 wherein determining the partitioning for a macroblock comprises approximating the cost of each partition in parallel.
17. The method of claim 1 wherein performing one or more refinement searches further comprises performing each of the one or more refinement searches across a plurality of macroblocks in parallel.
18. The method of claim 1 wherein the distortion value comprises at least one of: a sum of absolute differences (SAD); a sum of squared errors (SSE); or a Hadamard transform.
19. A method of encoding a block of data of a frequency transform, the method comprising:
assigning a worth to a first plurality of data, of the block of data, according to a first algorithm;
assigning a worth to a second plurality of data, of the block of data, according to a second algorithm, wherein the second plurality of data is of a lower frequency than the first plurality of data;
assigning a worth to the block of data based, at least in part, on the worth of the first plurality of data and the worth of the second plurality of data;
adjusting a value of the block of data based, at least in part, on worth assigned to the block of data.
20. The method of claim 19 wherein assigning a worth to the block of data comprises assigning a worth to the block of data based, at least in part, on a summation of the worth of the first plurality of data and the worth of the second plurality of data.
21. The method of claim 19 wherein assigning a worth to a first plurality of data comprises assigning a worth based, at least in part, on a summation of data values of the first plurality of data.
22. The method of claim 21 wherein the summation of data values is scaled by an adjustable factor.
23. The method of claim 19 wherein assigning a worth to the second plurality of data comprises assigning a worth based, at least in part, on a summation of worth of non-zero data values of the second plurality of data.
24. The method of claim 23 further comprising assigning a worth to each of the non-zero data values based, at least in part, on a number of consecutive data values equal to zero preceding each of the non-zero data values.
25. The method of claim 19 wherein adjusting a value of the block of data comprises adjusting the value of each data value of the block of data.
26. The method of claim 25 wherein adjusting each data value comprises assigning a zero value to each data value of the block of data.
27. The method of claim 19 wherein the block of data is corresponds to a block of pixels.
28. The method of claim 27 wherein the block of pixels is a 4\xd74 block.
29. A method of packing data words into a bitstream, the method comprising:
packing a first plurality of data words onto a first sub-stream;
packing a second plurality of data words onto a second sub-stream, wherein packing the first and second pluralities of data words is performed in parallel; and
packing the first and second sub-streams into a single bitstream.
30. The method of claim 29 wherein packing the first and second sub-streams into a single bitstream comprises storing the first and second sub-streams in a variable record length memory system.
31. The method of claim 29 wherein packing the first and second sub-streams into a single bitstream comprises transposing the first and second sub-streams across hardware resources intended for parallel processing.
32. The method of claim 31 further comprising assembling the first and second sub-streams in a partitioned memory.
33. The method of claim 29 wherein packing the first and second sub-streams into a single bitstream comprises writing one or more valid elements of each of the first and second sub-streams directly to a partitioned memory.
34. The method of claim 33 further comprising storing an index associated with each of the one or more valid elements of each of the first and second sub-streams, wherein the indices are stored directly to a partitioned memory.
35. The method of claim 34 further comprising storing the first and second sub-streams from the partitioned memory in an ordered bitstream in a DRAM based, at least in part, on the indices.
36. A video coding system comprising:
means for identifying a first plurality of candidates in a reference frame, wherein the first plurality of candidates is substantially smaller than the total reference frame;
means for reducing the first plurality of candidates to one or more trimmed candidates;
means for loading the one or more trimmed candidates from a storage element;
means for measuring one or more distortion values based, at least in part, on the trimmed candidates; and
means for encoding motion data based, at least in part, the one or more distortion values.
37. A system for encoding data, the system comprising:
means for assigning a worth to a first plurality of data, of a block of data, according to a first algorithm;
means for assigning a worth to a second plurality of data, of the block of data, according to a second algorithm, wherein the second plurality of data is of a higher frequency than the first plurality of data;
means for assigning a worth to the block of data based, at least in part, on the worth of the first plurality of data and the worth of the second plurality of data;
means for adjusting a value of the block of data based, at least in part, on the worth assigned to the block of data.
38. A system for packing data into a bitstream, the system comprising:
means for packing a first plurality of data words onto a first sub-stream;
means for packing a second plurality of data words onto a second sub-stream, wherein the first and second pluralities of data words are packed in parallel; and
means for packing the first and second sub-streams into a single bitstream.
39. The system of claim 38 further comprising storage means for storing a variable record length.
40. A computer-readable medium carrying one or more sequences of instructions which, when executed by one or more processors, causes the one or more processors to:
identifying a first plurality of candidates in a reference frame, wherein the first plurality of candidates is substantially smaller than the total reference frame;
reducing the first plurality of candidates to one or more trimmed candidates;
loading the one or more trimmed candidates from a storage element;
measuring one or more distortion values based, at least in part, on the trimmed candidates; and
encoding motion data based, at least in part, the one or more distortion values utilize an approximation for ensuring that a route can be found for one or more open communications.
41. A system comprising:
a processing entity;
a memory coupled to said processing entity having data stored therein and having program code stored therein which, when executed by said processing entity, causes said processing entity to:
identify a first plurality of candidates in a reference frame, wherein the first plurality of candidates is substantially smaller than the total reference frame;
reduce the first plurality of candidates to one or more trimmed candidates;
load the one or more trimmed candidates from a storage element;
measure one or more distortion values based, at least in part, on the trimmed candidates; and
encode motion data based, at least in part, the one or more distortion values.
42. A system comprising:
a processing entity;
a memory coupled to said processing entity having data stored therein and having program code stored therein which, when executed by said processing entity, causes said processing entity to:
assign a worth to a first plurality of data, of a block of data, according to a first algorithm;
assign a worth to a second plurality of data, of the block of data, according to a second algorithm, wherein the second plurality of data is of a higher frequency than the first plurality of data;
assign a worth to the block of data based, at least in part, on the worth of the first plurality of data and the worth of the second plurality of data;
adjust a value of the block of data based, at least in part, on worth assigned to the block of data.
43. A system comprising:
a processing entity;
a memory coupled to said processing entity having data stored therein and having program code stored therein which, when executed by said processing entity, causes said processing entity to:
pack a first plurality of data words onto a first sub-stream;
pack a second plurality of data words onto a second sub-stream; and
pack the first and second sub-streams into a single bitstream.