1. A medical resource storage and management apparatus comprising:
a horizontal-bridging member which is provided with a series of hanger member fitting parts operable to hang and arrange a large number of medical resources;
a hanger member which is fitted to the hanger member fitting part and is pivotally moved depending on whether a medical resource is hung;
a medical resource detecting member which is provided in each of the hanger member fitting parts so as to detect whether a medical resource is hung in an associated location in accordance with the pivotal movement of the associated hanger member;
a retrieval guidance member for visual confirmation provided in each of the hanger member fitting parts; and
a control unit which manages the storage status of the medical resources, based on the detection by the medical resource detecting member, and which operates the retrieval guidance member in response to an input designating retrieval, wherein,
at the time of hanging a medical resource, the pivotal movement of the hanger member causes the engaging part engaged with the medical resource to be lowered, and, at the time of retrieving a medical resource, the pivotal movement causes the engaging part to be elevated and moved toward an operator.
2. The medical resource storage and management apparatus according to claim 1, wherein the pivotal movement of the hanger member is based on the displacement between the center of gravitation and the pivot center.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A chopper circuit comprising a delay circuit that delays a received control signal and a difference detection circuit that detects a difference between a control signal delayed by said delay circuit and the received control signal, wherein:
a first threshold, based on which said delay circuit checks a change in the received control signal, and a second threshold, based on which said difference detection circuit checks a change in the received control signal, are realized with a common threshold.
2. The chopper circuit as claimed in claim 1, wherein said delay circuit comprises an odd number of stages of NOR gates connected in series with one another.
3. The chopper circuit as claimed in claim 2, wherein the first threshold, based on which said delay circuit checks a change in the received control signal, and the second threshold, based on which said difference detection circuit checks a change in the received control signal are realized with a threshold to be used by a common logic circuit that receives the control signal.
4. The chopper circuit as claimed in claim 3, wherein, said difference detection circuit comprises:
a first transistor of a first conductivity type having a source connected to a first power line and a gate supplied with the control signal;
a second transistor of the first conductivity type having a source connected to the first power line and a gate supplied with an output signal of said delay circuit;
a third transistor of a second conductivity type having a drain connected to drains of said first and second transistors respectively and a gate supplied with the output signal of said delay circuit;
a fourth transistor of the second conductivity type having a source connected to a second power line and a gate supplied with the control signal; and
a fifth transistor of the first conductivity type connected in common to each of the first power line, a source of said third transistor, and a drain of said fourth transistor, wherein said fourth and fifth transistors constitute an inversion logic gate on a first stage in said delay circuit.
5. The chopper circuit as claimed in claim 4, wherein said inversion logic gate on the first stage is realized with an inverter.
6. The chopper circuit as claimed in claim 4, wherein said inversion logic gate on the first stage is realized with a NAND gate having a first input terminal supplied with the control signal and a second input terminal supplied with an enabling signal.
7. The chopper circuit as claimed in claim 4, wherein said delay circuit comprises an odd number of stages of inverters.
8. The chopper circuit as claimed in claim 5, wherein said delay circuit comprises a NAND gate having a first input terminal supplied with an output signal of said inversion logic gate and a second input terminal supplied with an enabling signal.
9. The chopper circuit as claimed in claim 3, wherein, said difference detection circuit comprises:
a first transistor of a first conductivity type having a source connected to a first power line and a gate supplied with a reset signal;
a second transistor of a second conductivity type having a drain connected to a drain of said first transistor and a gate supplied with an output signal of said delay circuit; and
a NOR gate having a first input terminal supplied with an output of an inverter which is connected to a common drain of said first and second transistors, and a second input terminal supplied with the control signal, wherein said NOR gate realizes said inversion logic gate on the first stage in said delay circuit.
10. The chopper circuit as claimed in claim 3, wherein, said difference detection circuit comprises:
a first transistor of a first conductivity type having a source connected to a first power line and a gate supplied with a reset signal;
a second transistor of a second conductivity type having a drain connected to a drain of said first transistor and a gate supplied with an output signal of said delay circuit; and
an inverter that receives the control signal, said inverter realizing said inversion logic gate on a first stage in said delay circuit, and wherein said difference detection circuit comprises:
a NOR gate having a first input terminal supplied with an output of said inverter which is connected to a common drain of said first and second transistors, and a second input terminal supplied with an output signal of the first stage of said inversion logic gate via another inversion logic gate.
11. The chopper circuit as claimed in claim 10, wherein said another inversion logic gate comprises a NAND gate having a first input terminal supplied with the output signal of said inversion logic gate, and a second input terminal supplied with an enabling signal.
12. The chopper circuit as claimed in claim 1, wherein the control signal is a clock signal, and said chopper circuit is a clock chopper circuit.