1. A detector for providing a low battery voltage indication comprising:
a stable voltage reference and comparator circuit for comparing the battery voltage and the voltage reference;
switch means to switch between a first operational state and a second operational state;
a switched capacitor circuit to store charges related to the battery voltage and the reference voltage in each operational state; and
a clock to initiate switching between the first and second states; wherein an output from the comparator during the second state indicates whether the battery voltage is below a preset threshold.
2. A detector as defined in claim 1 wherein said stable voltage reference is a bandgap reference circuit.
3. A detector as defined in claim 2 wherein said bandgap reference circuit comprises a pair of bipolar transistors supplied with a first current density in said first state and a second greater current density in said second state.
4. A detector as defined in claim 1 wherein said first operational state is a precharge phase and said second operational state is an evaluation phase.
5. A detector as defined in claim 1 fabricated on an integrated circuit (IC) employing CMOS technology.
6. A detector as defined in claim 5 wherein said comparator is an operational amplifier.
7. A detector as defined in claim 6 wherein offset voltages due to first and second inputs to said operational amplifier are cancelled by said switched capacitor circuit.
8. A detector as defined in claim 1 wherein capacitors in said switched capacitor circuit define a weighting factor for establishing said threshold.
9. A detector as defined in claim 1 wherein said threshold (Vmin) is set such that:
Vmin>VBEK1VBEK2BAT
where:
Vmin is the threshold value
VBE is the base to emitter voltage across a first transistor of the bandgap reference;
VBE is the difference between base to emitter voltages in two bandgap transistors having different current densities;
VBAT is the battery voltage;
K1 is a first scaling factor; and
K2 is a second scaling factor.
10. A detector as defined in claim 9 having three capacitors (C1, C2 and C3) wherein K1 and K2 are determined by said capacitors according to the ratios K1C1C2C3 and K2C1C3.
11. A detector as defined in claim 1 wherein said bandgap reference circuit comprises three bipolar transistors with a first switchable current source is supplied to one transistor and a second current source is supplied to the other two transistors.
12. A method of detecting a low battery voltage supplied to an integrated circuit comprising:
providing a stable voltage reference and comparator circuit for comparing battery voltage against the reference voltage;
providing a capacitor circuit for storing charges associated with the battery voltage and the reference voltage;
providing switching means to switch between a first phase wherein said capacitors are charged to a first voltage level and a second phase wherein said capacitors are charged to a second level; and
comparing said first and second levels to determine whether said battery voltage is above or below a preset threshold.
13. The method as defined in claim 12 wherein said switching means are MOS devices.
14. The method of claim 12 wherein said preset threshold (Vmin) is such that:
VminVrefK*Vbat
where:
Vref is the reference voltage
Vbat is the battery voltage; and
K is a scaling factor
15. The method of claim 14 wherein said stable voltage reference is a bandgap cell having a value of approximately 1.2 volts and Vmin is approximately 1.2K.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A test apparatus for testing a memory under test accessed in page-units and having a storage region that can be disabled in block-units that contain defects, each block including a plurality of pages, the test apparatus comprising:
a bad block memory that stores a plurality of pieces of fail information in association with the blocks of the memory under test, each piece of fail information indicating whether there is a defect in the corresponding block;
a data writing section that writes a test data sequence to a page under test of the memory under test;
a data reading section that reads the test data sequence written to the page under test;
a comparing section that compares the read data sequence to the written data sequence;
a fail detecting section that detects whether there is a defect corresponding to each of a plurality of predetermined fail conditions serving as conditions for determining whether there is a defect in the page under test, and outputs the detection result as a fail signal; and
an updating section that updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to fail conditions allocated in advance to the plurality of pieces of fail information associated with the block including the page under test.
2. The test apparatus according to claim 1, further comprising an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information, wherein
the updating section updates the plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to fail conditions allocated according to the allocation information.
3. The test apparatus according to claim 2, wherein
the fail detecting section includes:
a plurality of fail detectors that detect different defects in the page under test based on at least one of (i) the comparison result of the comparing section, (ii) time needed to write the data sequence, and (iii) time needed to read the data sequence; and
a plurality of selecting sections that (i) are provided to correspond respectively to the plurality of pieces of fail information, (ii) each select a fail detector to which the corresponding fail information is allocated, based on the allocation register, and (iii) each output a fail signal generated based on a detection result from the selected fail detector, wherein
the updating section updates the plurality of pieces of fail information associated with the block including the page under test using the plurality of fail signals output by the plurality of selecting sections.
4. The test apparatus according to claim 1, further comprising:
a disable register that stores disable information designating, from among the plurality of pieces of fail information, pieces of fail information associated with a defect for which the block is to be disabled;
a mask processing section that reads, from the bad block memory, the plurality of pieces of fail information associated with the block including the page under test, and that cancels testing of the page under test if the pieces of fail information designated by the disable register from among the plurality of pieces of read fail information indicate that there is a defect in the block.
5. The test apparatus according to claim 4, wherein
the mask processing section includes:
a fail information selecting section that selects the pieces of fail information designated by the disable register from among the plurality of pieces of read fail information; and
a mask generating section that generates a mask signal indicating whether to cancel testing of the page under test, based on the selected pieces of fail information, wherein
when the mask signal indicating cancellation of testing of the page under test is received, the data writing section cancels writing of the test data sequence to this page.
6. The test apparatus according to claim 4, wherein
the mask processing section includes:
a fail information selecting section that selects the pieces of fail information designated by the disable register from among the plurality of pieces of read fail information; and
a mask generating section that generates a mask signal indicating whether to cancel testing of the page under test, based on the selected pieces of fail information, wherein
when the mask signal indicating cancellation of testing of the page under test is received, the comparing section does not detect a discrepancy between the data sequence read from this page and the data sequence written to this page.
7. A test apparatus for testing a memory under test accessed in page-units and having a storage region that can be disabled in block-units that contain defects, each block including a plurality of pages, the test apparatus comprising:
a bad block memory that stores a plurality of pieces of fail information in association with the blocks of the memory under test, each piece of fail information indicating whether there is a defect in the corresponding block;
a data writing section that writes a test data sequence to a page under test of the memory under test;
a data reading section that reads the test data sequence written to the page under test;
a comparing section that compares the read data sequence to the written data sequence;
a fail detecting section that detects whether there is a defect corresponding to a plurality of fail conditions for determining whether there is a defect in the page under test, and outputs the detection results as fail signals;
an updating section that updates a plurality of pieces of fail information associated with the block including the page under test using a plurality of the fail signals;
a disable register that stores disable information designating, from among the plurality of pieces of fail information, pieces of fail information associated with a defect for which the block is to be disabled; and
a mask processing section that reads, from the bad block memory, the plurality of pieces of fail information associated with the block including the page under test, and that cancels testing of the page under test if the pieces of fail information designated by the disable register from among the plurality of pieces of read fail information indicate that there is a defect in the block.
8. A method for testing, with a test apparatus, a memory under test accessed in page-units and having a storage region that can be disabled in block-units that contain defects, each block including a plurality of pages, the method comprising:
causing a bad block memory provided to the test apparatus to store a plurality of pieces of fail information in association with the blocks of the memory under test, each piece of fail information indicating whether there is a defect in the corresponding block;
writing a test data sequence to a page under test of the memory under test;
reading the test data sequence written to the page under test;
comparing the read data sequence to the written data sequence;
detecting whether there is a defect corresponding to each of a plurality of predetermined fail conditions serving as conditions for determining whether there is a defect in the page under test, and outputting the detection result as a fail signal; and
updating a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to fail conditions allocated in advance to the plurality of pieces of fail information associated with the block including the page under test.
9. A method for testing, with a test apparatus, a memory under test accessed in page-units and having a storage region that can be disabled in block-units that contain defects, each block including a plurality of pages, the method comprising:
storing, in a bad block memory provided to the test apparatus, a plurality of pieces of fail information in association with the blocks of the memory under test, each piece of fail information indicating whether there is a defect in the corresponding block;
writing a test data sequence to a page under test of the memory under test;
reading the test data sequence written to the page under test;
comparing the read data sequence to the written data sequence;
detecting whether there is a defect corresponding to a plurality of fail conditions for determining whether there is a defect in the page under test, and outputting the detection results as fail signals;
updating a plurality of pieces of fail information associated with the block including the page under test using a plurality of the fail signals;
storing, in a disable register provided to the test apparatus, disable information designating, from among the plurality of pieces of fail information, pieces of fail information associated with a defect for which the block is to be disabled;
prior to writing the test data sequence to the page under test, reading, from the bad block memory, the plurality of pieces of fail information associated with the block including the page under test; and
canceling testing of the page under test if the pieces of fail information designated by the disable register from among the plurality of pieces of read fail information indicate that there is a defect in the block.
10. A test apparatus that tests a memory under test, which is a flash memory including a plurality of blocks that each include a plurality of pages, the test apparatus comprising:
a fail detecting section that detects a defect in (i) reading or writing of page-units of data from or to the memory under test or (ii) a process for deleting a block-unit of data from the memory under test, and outputs the detection result as a fail signal;
a control apparatus that divides the memory under test into a plurality of grades based on the fail signal output by the fail detecting section, wherein
the fail detecting section includes a fail detector detecting at least one of (i) whether error correction is possible with any of a plurality of different types of error correction codes, (ii) whether or not a program time, which is a time needed from when the writing begins to complete the writing, is greater than or equal to a reference value and (iii) whether or not a time needed to delete a block-unit of data is greater than or equal to a reference value.
11. The test apparatus according to claim 10, further comprising a mask processing section that cancels testing of a block on a condition that the block is indicated as being a defective block based on the fail signal output by the fail detecting section.