What is claimed is:
1. A method for forming a self-aligned gate structure around an emitter tip, comprising:
forming a cathode on a substrate, the cathode having an emitter tip;
forming an insulator layer over the cathode and the emitter tip;
ion etching the insulator layer; and
forming a gate layer on the insulator layer.
2. The method of claim 1, wherein forming a gate layer includes:
depositing a refractory metal on the insulator layer; and
using a chemical mechanical planarization (CMP) process on the refractory metal in order to expose a portion of the insulator layer surrounding the emitter tip.
3. The method of claim 2, wherein the method further includes removing a portion of the insulator layer surrounding the emitter tip in order to uncover the emitter tip.
4. The method of claim 1, wherein ion etching the insulator layer includes using an ion gun as a source of the ions.
5. The method of claim 1, wherein ion etching the insulator layer includes using an Argon plasma ion source.
6. The method of claim 1, wherein ion etching the insulator layer includes using an Oxygen plasma ion source.
7. The method of claim 1, wherein the method further includes coating the emitter tip with a low work function material.
8. The method of claim 1, wherein forming a cathode on a substrate includes forming the cathode on a glass substrate.
9. The method of claim 1, wherein forming a cathode on a substrate includes forming the cathode on a doped silicon material substrate.
10. The method of claim 1, wherein forming a gate layer includes forming a molybdenum (Mo) gate layer.
11. The method of claim 1, wherein forming a gate layer includes forming a tungsten (W) gate layer.
12. The method of claim 1, wherein forming a gate layer includes forming a titanium (Ti) gate layer.
13. A method for forming a self-aligned gate structure around an emitter tip, comprising:
forming a cathode on a substrate, the cathode having an emitter tip;
forming an insulator layer over the cathode and the emitter tip;
ion etching the insulator layer; and
forming a gate layer on the insulator layer, wherein forming a gate layer includes;
depositing a refractory metal on the insulator layer; and
using a chemical mechanical planarization (CMP) process on the refractory metal in order to expose a portion of the insulator layer surrounding the emitter tip.
14. A method for forming a self-aligned gate structure around an emitter tip, comprising:
forming a cathode on a substrate, the cathode having an emitter tip;
forming an insulator layer over the cathode and the emitter tip;
ion etching the insulator layer using an ion gun as a source of the ions; and
forming a gate layer on the insulator layer, wherein forming a gate layer includes;
depositing a refractory metal on the insulator layer; and
using a chemical mechanical planarization (CMP) process on the refractory metal in order to expose a portion of the insulator layer surrounding the emitter tip.
15. A method for forming a self-aligned gate structure around an emitter tip, comprising:
forming a cathode on a substrate, the cathode having an emitter tip;
forming an insulator layer over the cathode and the emitter tip;
ion etching the insulator layer using an Argon plasma ion source; and
forming a gate layer on the insulator layer, wherein forming a gate layer includes;
depositing a refractory metal on the insulator layer; and
using a chemical mechanical planarization (CMP) process on the refractory metal in order to expose a portion of the insulator layer surrounding the emitter tip.
16. A method for forming a self-aligned gate structure around an emitter tip, comprising:
forming a cathode on a glass substrate, the cathode having an emitter tip;
forming an insulator layer over the cathode and the emitter tip;
ion etching the insulator layer using an Argon plasma ion source; and
forming a gate layer on the insulator layer, wherein forming a gate layer includes; depositing a refractory metal on the insulator layer;
using a chemical mechanical planarization (CMP) process on the refractory metal in order to expose a portion of the insulator layer surrounding the emitter tip;
removing a portion of the insulator layer surrounding the emitter tip in order to uncover the emitter tip; and
coating the emitter tip with a low work function material.
17. A method of forming a field emission device on a substrate, comprising:
forming a cathode emitter tip in a cathode region of the substrate;
forming a gate insulator layer on the emitter tip and the substrate;
using an ion etch process in order to reduce the thickness of the gate insulator layer in the cathode region more rapidly than in the isolation region;
forming a gate on the gate insulator layer; and
forming an anode opposite the emitter tip.
18. The method of claim 17, wherein using an ion etch process to reduce the thickness of the gate insulator layer includes forming a buffer layer on the cathode emitter tip prior to using the ion etch process in order to protect the emitter tip from over etching.
19. The method of claim 18, wherein forming a buffer layer includes forming a dielectric layer of silicon nitride (Si3N4).
20. The method of claim 17, wherein forming the cathode emitter tip includes forming a polysilicon cone.
21. The method of claim 17, wherein forming the cathode emitter tip includes forming a metal silicide on a polysilicon cone.
22. The method of claim 17, wherein forming a gate includes:
depositing a conductive material on the gate insulator layer; and
using a chemical mechanical planarization (CMP) process on the conductive material in order to expose a portion of the gate insulator layer surrounding the emitter tip.
23. The method of claim 17, wherein forming a field emitter device on a substrate includes forming the field emitter device on a glass substrate.
24. The method of claim 17, wherein forming a field emitter device on a substrate includes forming the field emitter device on a doped silicon material substrate.
25. The method of claim 17, wherein forming a gate includes forming a gate from a refractory metal.
26. The method of claim 17, wherein forming a gate includes forming a gate from doped polysilicon.
27. A method of forming a field emission device on a substrate, comprising:
forming a cathode emitter tip in a cathode region of the substrate;
forming a gate insulator layer on the emitter tip and the substrate;
using an ion etch process in order to reduce the thickness of the gate insulator layer in the cathode region more rapidly than in the isolation region;
forming a gate on the gate insulator layer, wherein forming a gate includes;
depositing a conductive material on the gate insulator layer; and
using a chemical mechanical planarization (CMP) process on the conductive material in order to expose a portion of the gate insulator layer surrounding the emitter tip; and
forming an anode opposite the emitter tip.
28. The method of claim 27, wherein using an ion etch process to reduce the thickness of the gate insulator layer includes forming a buffer layer on the cathode emitter tip prior to using the ion etch process in order to protect the emitter tip from over etching.
29. The method of claim 28, wherein forming a buffer layer includes forming a dielectric layer of silicon nitride (Si3N4).
30. The method of claim 27, wherein forming the cathode emitter tip includes forming a polysilicon cone.
31. The method of claim 27, wherein forming a field emitter device on a substrate includes forming the field emitter device on a glass substrate.
32. The method of claim 27, wherein forming a field emitter device on a substrate includes forming the field emitter device on a doped silicon material substrate.
33. A method of forming a field emission device on a glass substrate, comprising:
forming a cathode emitter tip in a cathode region of the substrate, wherein forming the cathode emitter tip includes forming a polysilicon cone;
forming a gate insulator layer on the emitter tip and the substrate;
using an ion etch process in order to reduce the thickness of the gate insulator layer in the cathode region more rapidly than in the isolation region, wherein the ion etch process further includes;
forming a dielectric layer of silicon nitride (Si3N4) on the cathode emitter tip prior to using the ion etch process in order to protect the emitter tip from over etching;
forming a gate on the gate insulator layer, wherein forming a gate includes;
depositing a conductive material on the gate insulator layer; and
using a chemical mechanical planarization (CMP) process on the conductive material in order to expose a portion of the gate insulator layer surrounding the emitter tip; and
forming an anode opposite the emitter tip.
34. The method of claim 33, wherein depositing a conductive material includes depositing a refractory metal.
35. The method of claim 33, wherein depositing a conductive material includes depositing doped polysilicon.
36. A field emitter array, comprising:
a number of cathodes formed in rows along a substrate;
a gate insulator formed along the substrate and surrounding the cathodes;
a number of gate lines formed on the gate insulator; and
a number of anodes formed in columns orthogonal to and opposing the rows of cathodes, the field emitter array formed by a method comprising:
forming a number of cathode emitter tips in cathode regions of the substrate;
forming a gate insulator layer on the emitter tips and the substrate, wherein forming the gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate;
forming a number of gate lines on the gate insulator layer; and
forming a number of anodes opposite the emitter tips.
37. The field emitter array of claim 36, wherein the number of gate lines and the number of cathodes are formed using a self-aligned technique.
38. The field emitter array of claim 36, wherein the number of cathodes include polysilicon cones.
39. The field emitter array of claim 36, wherein the number of cathodes include metal silicides on the polysilicon cones.
40. The field emitter array of claim 36, wherein the substrate includes glass.
41. The field emitter array of claim 36, wherein the number of gate lines include refractory metals.
42. The field emitter array of claim 36, wherein the number of gate lines include doped polysilicon.
43. A flat panel display, comprising:
a field emitter array formed on a glass substrate, wherein the field emitter array includes:
a number of cathodes formed in rows along the substrate;
a gate insulator formed along the substrate and surrounding the cathodes;
a number of gate lines formed on the gate insulator; and
a number of anodes formed in columns orthogonal to and opposing the rows of cathodes, wherein the anodes include multiple phosphors, and wherein the intersection of the rows and columns form pixels, the field emitter array formed by a method comprising:
forming a number of cathode emitter tips in cathode regions of the substrate;
forming a gate insulator layer on the emitter tips and the substrate, wherein forming the gate insulator layer includes ion etching the insulator layer such that the insulator layer is formed thinner around the emitter tips than in an isolation region of the substrate;
forming a number of gate lines on the gate insulator layer; and
forming a number of anodes opposite the emitter tips;
a row decoder and a column decoder each coupled to the field emitter array in order to selectively access the pixels; and
a processor adapted to receiving input signals and providing the input signals to the row and column decoders.
44. The flat panel display of claim 43, wherein the number of gate lines and the number of cathodes are formed using the self-aligned technique.
45. The flat panel display of claim 43, wherein the number of cathodes include metal silicides on the polysilicon cones.
46. The flat panel display of claim 43, wherein the number of gate lines include refractory metals.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A closure comprising a wall defining an aperture and a membrane frangibly connected to the wall and closing the aperture, the frangible connection between the membrane and the wall lying in a plane which is inclined to a plane perpendicular to an axis of the aperture.
2. A closure in accordance with claim 1, wherein the aperture comprises a bore having opposite ends.
3. A closure in accordance with claim 2, wherein the opposite ends of the bore occupy parallel planes.
4. A closure in accordance with claim 1, wherein means is provided attached to the membrane with which to tear the membrane from the wall.
5. A closure in accordance with claim 4, wherein the aperture comprises a bore having opposite ends and, prior to use, said means occupy a position wholly within the bore.
6. A closure in accordance with claim 4, wherein said means is attached to a surface of the membrane facing one of said ends, said means being attached to a peripheral portion of the membrane at a location where the membrane is closest to said one end.
7. A closure in accordance with claim 4, wherein said means comprises a pull-ring.
8. A closure in accordance with claim 7, wherein the aperture comprises a bore having opposite ends and said pull-ring comprises an annular band which extends axially between a plane perpendicular to an axis of the bore and a plane proximate the inclined plane occupied by the frangible connection.
9. A closure in accordance with claim 1, wherein the membrane comprises a peripheral portion and a concave central portion.
10. A closure in accordance with claim 9, wherein the aperture comprises a bore having opposite ends and the concave central portion extends away from one of said ends but does not extend beyond a plane defined by the other of said ends.
11. A closure in accordance with claim 6, wherein the wall defining the bore is strengthened intermediate the membrane and the end opposite said one end.
12. A closure in accordance with claim 2, wherein the bore is of circular cross-section such that a plane perpendicular to the axis of the bore comprises a radial plane.
13. A closure in accordance with claim 1, wherein the frangible connection between the wall and the membrane defines an ellipse.
14. A closure in accordance with claim 6, wherein the bore decreases in internal diameter between said one end and the membrane.
15. A closure in accordance with claim 2, further comprising a cap having a sealing surface, the sealing surface being adapted to be received within one end of the bore to sealingly engage the wall at a location intermediate the membrane and said one end.