1. A semiconductor memory device comprising:
a first inputoutput pin;
a second inputoutput pin; and
a memory core coupled to the first and second inputoutput pins, the semiconductor memory device configured to perform bi-directional communication between the memory core and a host through one of the first and second inputoutput pins in a normal mode, the semiconductor memory device configured to communicate from test equipment to the memory core through the first inputoutput pin in a test mode, the semiconductor memory further configured to communicate from the memory core to the test equipment through the second inputoutput pin in the test mode.
2. The semiconductor memory device of claim 1, further comprising:
a first inputoutput buffer coupled to the first inputoutput pin; and
a second inputoutput buffer coupled to the second inputoutput pin.
3. The semiconductor memory device of claim 2, wherein the first inputoutput buffer comprises:
a first input buffer coupled to the first inputoutput pin; and
a first output buffer coupled to the first inputoutput pin.
4. The semiconductor memory device of claim 3, wherein the second inputoutput buffer comprises:
a second input buffer coupled to the second inputoutput pin; and
a second output buffer coupled to the second inputoutput pin.
5. The semiconductor memory device of claim 4, further comprising a controller coupled to the first output buffer and the second output buffer.
6. The semiconductor memory device of claim 5, the first output buffer being responsive to a first and second control signal output from the controller, the second output buffer being responsive to a third and fourth control signal output from the controller.
7. The semiconductor memory device of claim 6, wherein the first output buffer comprises:
a NAND gate, a first input of the NAND gate coupled to the memory core, a second input of the NAND gate coupled to receive the first control signal and;
a NOR gate, a first input of the NOR gate coupled to the memory core, a second input of the NOR gate coupled to receive the second control signal;
a PMOS pull-up transistor, a source of the PMOS pull-up transistor coupled to a power supply voltage source, a drain of the PMOS pull-up transistor coupled to and the first inputoutput pin, a gate of the PMOS pull-up transistor coupled to an output of the NAND gate; and
an NMOS pull-down transistor, a source of the NMOS pull-down transistor coupled to the first inputoutput pin, a drain of the NMOS pull-down transistor coupled to a ground voltage source, a gate of the NMOS pull-down transistor coupled to an output of the NOR gate.
8. The semiconductor of claim 7, wherein the first input of the NAND gate and the first input of the NOR gate are coupled to the memory core via the controller.
9. The semiconductor memory device of claim 6, wherein the second output buffer comprises:
a NAND gate, a first input of the NAND gate coupled to the memory core, a second input of the NAND gate coupled to receive the third control signal and;
a NOR gate, a first input of the NOR gate coupled to the memory core, a second input of the NOR gate coupled to receive the fourth control signal;
a PMOS pull-up transistor, a source of the PMOS pull-up transistor coupled to a power supply voltage source, a drain of the PMOS pull-up transistor coupled to and the second inputoutput pin, a gate of the PMOS pull-up transistor coupled to an output of the NAND gate; and
an NMOS pull-down transistor, a source of the NMOS pull-down transistor coupled to the second inputoutput pin, a drain of the NMOS pull-down transistor coupled to a ground voltage source, a gate of the NMOS pull-down transistor coupled to an output of the NOR gate.
10. The semiconductor of claim 9, wherein the first input of the NAND gate and the first input of the NOR gate are coupled to the memory core via the controller.
11. A memory module comprising:
a substrate; and
a plurality of memory devices assembled on the substrate, each of the memory devices having a first channel and a second channel, each of the plurality of memory devices configured to use a selected one of the first channel and the second channel for bi-directional communications with a host during normal operations, each of the plurality of memory devices configured to use the first channel to receive communications from a test device in a test mode.
12. The memory module of claim 11, each of the plurality of memory devices configured to use the second channel to transmit communications to the test device in the test mode.
13. The memory module of claim 11 wherein each of the memory devices includes a Ball Grid Array (BGA).
14. The memory module of claim 13, the first channel being associated with an Out of Band (OOB) pin, the second channel being associated with a mirrored OOB pin.
15. The memory module of claim 14, the OOB pin being in a first corner of the BGA, the mirrored OOB pin being in a second corner of the BGA, the second corner being opposite the first corner.
16. The memory module of claim 11 wherein the substrate is a double-sided substrate, a first portion of the plurality of memory devices being assembled to a first side of the double-sided substrate and a second portion of the plurality of memory devices being assembled to a second side of the double-sided substrate.
17. A method for controlling a memory device comprising:
determining whether the memory device is in a normal mode or a test mode;
if the device is in the normal mode, selecting one of a first channel and a second channel; and
if the device is in the normal mode, configuring the selected channel for bi-directional communications with a host.
18. The method of claim 17 wherein the first channel is associated with a first inputoutput buffer, the second channel is associated with a second inputoutput buffer, and configuring the selected channel includes outputting at least one control signal to at least one of the first and second inputoutput buffers based on the selected channel.
19. The method of claim 17, further comprising:
if the memory device is in the test mode, configuring the first channel to receive first signals from a test device; and
if the memory device is in the test mode, configuring the second channel to transmit second signals to the test device.
20. The method of claim 19 wherein the first channel is associated with a first inputoutput buffer, the second channel is associated with a second inputoutput buffer, configuring the first channel includes outputting at least one control signal to the first inputoutput buffer, and configuring the second channel includes outputting at least one other control signal to the second inputoutput buffer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A swim trainingfull body exercise machine for swimmers and non-swimmers able to give users a rhythmic, challenging and sustained work-out having its design and some major parts thereof named after the anatomy of a shark comprising a \u201cY\u201d shaped front Pectoral support section,
middle rectangle support section with locking device and double horizontal stem rods attached to
an inverted \u201cT\u201d shaped rear section known as the Pelvic cross section having rollers on its under side, with a sway T- bar anchored in its’ middle, connecting two elongated paddles known as the,
Caudal kicker system fins with Caudal kicker mechanisms attached to hold the residential or commercial foot harnesses,
a torso support pad affixed to a slightly curved glide bar rail system, and
a three part interconnected cable system featuring an outer, a central and a rear connection points starting with the hands and ending at the feet along a single cable per each opposite hand and foot connection.
2. A machine according to claim 1 wherein the user creates and controls the level of resistance through the mechanics of the machine representing applied tension physics creating tension force displacement when the body corresponds in competition from hand and foot resistance.
3. A machine according to claim 1 wherein a free moving part affixed along a cable system is moved by the tension of the cable.
4. A machine according to claim 3 wherein the users’ torso is supported horizontally on a support pad affixed to a glide bar rail system while the users’
each hand and opposite foot are attached to an opposite hand and foot harness which is connected to a
single cable passing through an outer cable pulley system, a central cable pulley system, and when tightened by opposite forces of the users’ hand and foot during a swim stroke causes the torso to move along the glide bar.
5. A machine according to claim 1 wherein has a front Pectoral section with folding support arms for storage.
6. A machine according to claim 1 can lock and unlock a pair of horizontal stem rods for adjustment to the length,
where as the rods pass through the locking device and are inserted into the middle rectangle support section, creating a collapsed position for storage and to aids the user in getting on and off the machine.
7. A machine according to claim 6 has locking device with a handle accessible to the user while lying in the prone position from the torso support pad.
8. A machine according to claim 1 wherein the rear inverted \u201cT\u201d shape section also known as pelvic cross section comprising a roller system having two smaller rollers housed on each outer fin tip and larger rollers housed in the middle just under the sway T-bar.
9. A machine according to claim 1 wherein having a single column support called the Dorsal column support being
erected from the middle of the front Pectoral support base, and having the central pulley system attached mid-way up its column, with its top serving as the base for the,
torso support pad hinge with a
glide bar rail system attached between the hinge and the torso pad.
10. A machine according to claim 9 wherein the front Pectoral support base arms each has attached to it the
outer spring pulley system featuring light tension spring pulleys, incorporated in the design for the completion of the swim stroke if needed.
11. A machine according to claim 4 and claim 1 wherein each hand has a
steel cable passing through an outer pulley system comprising a light tension spring pulley with a hand harness attachment with an inserted anchoring plate with steel D-ring hook latched to the cable which proceeds through a central pulley system and then attached to the foot harness of the Caudal kicker mechanism.
12. A machine in the alternative to claim 1 wherein having a curved glide bar can also have a non-curved glide bar.
13. A machine in the alternative to claim 11 wherein the cable can pass through the central pulley system and then through another pulley attached to the opposite side of the torso pad support, thus causing the pad to move during a simulated swim stroke, while the cable proceeds on to the caudal kicker system.
14. A machine in the alternative to claim 1 wherein having adjustable double horizontal stem rods with a locking device, can also use a solid horizontal rail system that allows the caudal kicker system to move forward and backwards with the use of cabled releaselocking pins affixed to the kicker system and pin holes at the front and rear of the rail