1. A method of aligning communication lanes interconnecting a transmitting device and a receiving device, the method comprising the steps of:
transmitting a training data on a first of the communication lanes by the transmitting device;
transmitting a short repetitive pattern on at least a second of the communication lanes by the transmitting device, the short repetitive pattern being shorter than a capture range of the receiving device;
transmitting deskew data, the deskew data including a portion of the training data from the first communication lane and a portion of the short repetitive pattern from the second communication lane; and
adjusting a preskew value at the transmitting device of the first communication lane until a feedback signal from the receiving device indicates that the communication lanes being trained are aligned, the feedback signal being a collective feedback signal indicative as to whether the plurality of communication lanes have been aligned;
wherein transmission of the portion of the short repetitive pattern enables the receiver to find a start of the deskew data from the second communication lane within the capture range on the second communication lane, to cause the receiver to determine that the second of the communication lanes is aligned.
2. The method of claim 1, wherein the step of transmitting a short repetitive pattern comprises transmitting a short repetitive pattern on at least all of the remaining unaligned communication lanes.
3. The method of claim 1, farther comprising the step of iterating the process for other communication lanes until all of the communication lanes are aligned.
4. The method of claim 1, wherein the second of the communication lanes is not aligned while transmitting the training data for the first communication lane.
5. The method of claim 1, wherein the preskew value is a delay value associated with a delay of the first communication lane.
6. The method of claim 1, wherein the communication lanes are implementing one of the SERDES-Framer Interface (SFI) standards.
7. The method of claim 1, further comprising the step of initially transmitting the short repetitive pattern on all of the communication lanes to cause the feedback signal from the receiving device to artificially initially indicate that all communication lanes are aligned.
8. A Field Programmable Gate Array (FPGA), comprising:
gate logic configured to implement a plurality of data lanes, an individually adjustable preskew delay for each said data lane, a feedback channel via which an alignment indication of all data lanes may be received, and a skew value adjuster via which the preskew delay for each data lane may be individually adjusted;
gate logic configured to enable the FPGA to isolate one of the data lanes for alignment by causing training data for the isolated data lane to be transmitted on the isolated data lane and causing a short fixed pattern to be transmitted on at least all unaligned data lanes,
the short repetitive pattern being shorter than a capture range of a receiving device enabling the receiver to find a start of the deskew data on the other unaligned data lanes within the capture range for those data lanes, to cause the receiver to artificially determine that the other unaligned data lanes are aligned;
gate logic configured to transmit deskew data, the deskew data including a portion of the training data to be used to align the isolated data lane as well as portions of the short repetitive pattern for each of the other unaligned data lanes;
gate logic configured to adjust the preskew value of the isolated data lane until a feedback signal from the receiving device indicates that the communication lanes are aligned, the feedback signal being a collective feedback signal indicative as to whether the plurality of communication lanes have been aligned.
9. The FPGA of claim 8, further comprising gate logic configured to construct a deskew channel containing a segment of data from each of the data lanes.
10. The FPGA of claim 8, further comprising gate logic configured to implement a training module to enable the FPGA to serially isolate the data lanes for alignment.
11. The FPGA of claim 8, further comprising an input configured to enable the FPGA to receive instructions to cause the FPGA to serially isolate the data lanes for alignment.
12. The FPGA of claim 8, wherein the FPGA is further configured to implement one of the SERDES-Framer Interface (SFI) standards.
13. The FPGA of claim 8, wherein the FPGA has sate logic configured to implement 16 data lanes.
14. The FPGA of claim 13, wherein the FPGA further comprises at least one multiplexer having an output connected to one of the 16 data lanes, a first input connected to a short pattern data source, a second input connected to a pseudorandom data source; and a third input connected to a data source.
15. The FPGA of claim 13, wherein the gate logic configured to enable the FPGA to isolate one of the data lanes for alignment is configured to initially cause the short fixed pattern to be transmitted on all 16 of the data lanes to clear the alignment indication from the feedback channel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
in a circuit substrate, forming a transistor device channel comprising a layer of channel silicon germanium (SiGe) material; and
forming a gate electrode for the transistor device, the gate electrode comprising a conductor material having a work function in a range between a valence energy band edge and a conduction energy band edge for silicon (Si).
2. The method of claim 1, wherein forming the channel includes depositing a sufficient thickness of a silicon germanium material to cause a compressive strain in the channel caused by a difference in lattice spacing of the circuit substrate material and a lattice spacing of at least one junction region proximate to the channel SiGe material causing a hydrostatic pressure on the channel SiGe material.
3. The method of claim 1, wherein forming the channel includes depositing a sufficient thickness of a silicon germanium material to cause a bi-axial compressive strain in the channel caused by a lattice spacing of the channel SiGe material being larger than a lattice spacing of a substrate material defining an interface surface of the substrate.
4. The method of claim 3, wherein forming the channel includes selective chemical vapor deposition (CVD) epitaxial growth of a layer of compressive strained SiGe material having a thickness of between 20 nanometers and 30 nanometers in thickness on a substrate having a thickness of between 1 and 3 micrometers in thickness.
5. The method of claim 3, wherein forming the channel comprises:
depositing a layer of channel SiGe material by a blanket deposition process;
forming an electronically insulating material in the channel material and the substrate between the interface surface and a surrounding region, after depositing the layer of channel SiGe material.
6. The method of claim 3, wherein forming the channel includes one of flowing during depositing with or doping after depositing with one of phosphorous, arsenic, and antimony to form an N-type channel region having an electrically negative charge.
7. The method of claim 1, wherein the conductor material is one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide.
8. The method of claim 1, wherein the work function is between 4.4 electron Volts and 4.7 electron Volts with respect to silicon.
9. The method of claim 1, wherein forming a gate electrode includes depositing a thickness of between 10 angstroms and 20 angstroms in thickness of the conductor material by one of an physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a Chemical vapor deposition (CVD) process.
10. The method of claim 1, further comprising:
forming a gate dielectric between the channel and the gate electrode, the gate dielectric comprising a gate dielectric material having a dielectric constant greater than a dielectric constant of silicon dioxide (SiO2).
11. The method of claim 10, wherein the gate dielectric material is one of silicon dioxide (SiO2), hafnium oxide (HfO), hafnium silicate (HfSiO4), hafnium disilicate (HfSi4O7), zirconium oxide (ZrO), zirconium silicate (ZrSiO4), tantalum oxide (Ta2O5).
12. The method of claim 10, wherein forming a gate dielectric comprises one of a Chemical vapor deposition (CVD) and an atomic layer deposition (ALD) of gate dielectric material to form a gate oxide layer having a thickness of between 1 nanometer and 4 nanometers in thickness and having a proper P-type work function for a channel of SiGe material.
13. The method of claim 10, wherein forming a gate electrode includes depositing a sufficient thickness of the conductor material to relieve electron depletion effects at an interface between the gate electrode and the gate dielectric.
14. The method of claim 10, further comprising:
forming an electronically insulating material between a first area of the substrate and a surrounding region prior to forming the channel;
forming the channel after forming the electronically insulating material;
forming the gate dielectric prior to forming the gate electrode; and
forming a first and second junction region in the channel adjacent to the gate electrode after forming the gate electrode.
15. The method of claim 14, wherein forming a first junction region and a second junction include depositing a sufficient thickness of a silicon germanium material having a larger lattice spacing than a lattice spacing of the circuit substrate material to cause a compressive strain in a range between 0.5 percent compression and 2.5 percent compression in the channel SiGe material.
16. The method of claim 1, wherein forming the gate electrode further includes:
forming a layer of semiconductor material over the conductor material;
one of flowing during forming with or doping after forming the layer of semiconductor material with one of boron and aluminum to form a P-type gate electrode having an electrically positive charge.
17. The method of claim 16, wherein forming the gate electrode includes depositing a sufficient thickness of the conductor material and a sufficient thickness of the semiconductor material to cause the transistor to have a threshold \u201cON\u201d voltage of between 0.2 volts and 0.3 volts.
18. The method of claim 16, wherein forming the gate electrode further includes:
patterning the semiconductor material with a hard mask {e.g, Si3N4};
removing a portion of the semiconductor material and a corresponding portion of the conductor material.
19. The method of claim 1, further comprising:
forming spacers superadjacent to the gate electrode;
wherein forming spacers includes removing a portion of the gate dielectric material;
removing a first and second portion of the channel SiGe material adjacent to and under the spacers to form a first and second junction region location;
depositing a silicon germanium junction material in each of the first and second junction region locations to form a first junction region and a second junction region;
wherein depositing a silicon germanium junction material in each of the first and second junction region locations includes one of flowing during depositing with or doping after depositing with one of boron and aluminum to form a P-type first junction region and a P-type second junction region having an electrically positive charge.
20. The method of claim 19, wherein flowing or doping include doping a sufficient amount of boron or aluminum to one of decrease resistivity, reduce shunt resistance, and increase the drive current of the P-type first junction region and the P-type second junction region.
21. The method of claim 19, wherein depositing a silicon germanium junction material in each of the first and second junction region locations includes flowing diborane during deposition.
22. An apparatus comprising:
a transistor device channel comprising a channel silicon germanium (SiGe) material on a circuit substrate;
a gate dielectric for the transistor device, the gate dielectric comprising a material having a dielectric constant greater than a dielectric constant of silicon dioxide; and
a gate electrode over the gate dielectric, the gate electrode comprising a conductor material having a work function in a range between a valence energy band edge and a conduction energy band edge for silicon (Si).
23. The apparatus of claim 22, wherein a hydrostatic pressure compressive strain is induced in the channel SiGe material by a lattice spacing of the circuit substrate material being smaller than a lattice spacing of at least one junction region.
24. The apparatus of claim 22, wherein the substrate is silicon (Si).
25. The apparatus of claim 22, wherein the channel is a layer of a Si1-YGeY material on an area of a Si1-XGeX material defining an interface surface of a substrate of graded relaxed silicon germanium material;
wherein the layer of Si1-YGeY material is under a compressive strain caused by a lattice spacing of the Si1-YGeY material being larger than a lattice spacing of the Si1-XGeX material at the interface surface.
26. The apparatus of claim 25, wherein X is in a range between 0.1 and 0.3 at the interface surface, and Y is greater than X by a range between 0.1 and 0.3.
27. An apparatus comprising:
an N-type PMOS transistor device channel comprising a layer of compressive strained silicon germanium material on a first area of a substrate material defining a first interface surface of a CMOS circuit substrate;
a gate dielectric for the PMOS transistor device, the gate dielectric having a dielectric constant greater than a dielectric constant of silicon dioxide;
a gate electrode for the PMOS transistor device over the gate dielectric for the PMOS transistor device, the gate electrode for the PMOS transistor device comprising a P-type semiconductor material on a conductor material having a work function in a range between a valence energy band edge and a conduction energy band edge for silicon (Si);
a P-type first junction region and a P-type second junction region in the N-type PMOS channel adjacent the gate electrode for the PMOS transistor device;
a P-type NMOS transistor device channel on a second area of the substrate material defining a different second interface surface of the CMOS circuit substrate separated from the first interface surface by an electronically insulating material;
a gate dielectric for the NMOS transistor device;
an N-type gate electrode for the NMOS transistor device over the gate dielectric for the NMOS transistor device;
an N-type first junction region and an N-type second junction region in the P-type NMOS channel adjacent the N-type gate electrode for the NMOS transistor device.
28. The apparatus of claim 27, wherein the PMOS transistor has a threshold \u201cON\u201d voltage of between 0.2 volts and 0.3 volts.
29. The apparatus of claim 27, wherein the substrate is a layer of graded relaxed silicon germanium material having a grading concentration of germanium that increases from 0 percent to between 10 percent and 30 percent at the first interface surface.