1. A method comprising:
receiving, by at least one processor, fixed positions of a plurality of nodes of a graph, the plurality of nodes and the fixed positions being always unadjustable so as to maintain compactness of the graph;
determining, by at least one processor, two or more curves to connect corresponding pairs of nodes of the plurality of nodes;
selecting, by at least one processor and based on a cost function and from the two or more curves, optimal curves for the corresponding pairs of nodes, the cost function for each curve being based at least on a distance of a farthest point on a curve from a straight line joining end points of the curve, the end points of the curve being positions of nodes to be connected by the curve; and
connecting, by at least one processor when a possible connecting of the corresponding pairs of nodes via respective straight lines results in more edge crossings than possible edge crossings associated with the optimal curves, the plurality of nodes by using the corresponding optimal curves, two or more connected nodes being connected to at least two other corresponding nodes.
2. The method of claim 1, wherein:
the two or more curves are determined for each pair of nodes of the plurality of nodes;
an optimal curve of the optimal curves is selected for each corresponding pair of nodes;
each pair of nodes is connected by a corresponding optimal curve of the optimal curves; and
each connected node of the two or more connected nodes is connected to at least two other nodes.
3. The method of claim 1, wherein the cost function is evaluated after the nodes become unadjustable.
4. The method of claim 1, wherein the nodes maintain orientation with respect to other nodes after the nodes are adjusted once and until the connecting is performed by the optimal curves so as to maintain the compactness of the graph.
5. The method of claim 1, further comprising:
rendering, by at least one processor, the connected plurality of nodes and the corresponding optimal curves in an output device.
6. The method of claim 1, wherein the optimal curves are associated with a maximum acceptable value of the cost function.
7. The method of claim 1, wherein at least one of the optimal curves is a cubic curve.
8. The method of claim 1, wherein at least one of the optimal curves is a quadratic curve.
9. A non-transitory computer program product storing instructions that, when executed by at least one programmable processor, cause the at least one programmable processor to perform operations comprising:
receiving fixed positions of a plurality of nodes of a graph, the plurality of nodes and the fixed positions being unadjustable after being fixed once so as to maintain compactness of the graph;
determining two or more curves to connect corresponding pairs of nodes of the plurality of nodes;
selecting, based on a cost function and from the two or more curves, optimal curves for the corresponding pairs of nodes, the cost function for each curve being based at least on a distance of a farthest point on a curve from a straight line joining end points of the curve, the end points of the curve being positions of nodes to be connected by the curve; and
connecting the plurality of nodes by using the corresponding optimal curves when a connecting of the corresponding pairs of nodes via respective optimal curves results in less intersections of the corresponding optimal curves than intersections of respective straight lines if the corresponding pairs of nodes were to be connected via the respective straight lines instead of the corresponding optimal curves, two or more connected nodes being connected to at least two other corresponding nodes.
10. The computer program product of claim 9, wherein the cost function is evaluated after the nodes become unadjustable.
11. The computer program product of claim 9, wherein the nodes maintain orientation with respect to other nodes after the nodes are adjusted once and until the connecting is performed by the optimal curves so as to maintain the compactness of the graph.
12. The method of claim 1, wherein the unadjustable fixed positions of the nodes are located in a plurality of levels such that the connected plurality of nodes are arranged in the plurality of levels, the connected plurality of nodes displaying data specifying corresponding ranges for values of a plurality of health parameters, two or more health parameters being associated with a plurality of corresponding nodes at each corresponding level.
13. The method of claim 12, wherein the plurality of health parameter comprise glucose, body mass index, age, insulin, pedigree, pregnancies, blood pressure, and triceps.
14. The computer program product of claim 9, wherein the connected plurality of nodes are arranged in different levels associated with respective health parameters comprising data associated with one or more of: glucose, body mass index, age, insulin, pedigree, pregnancies, blood pressure, and triceps.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pressure contact type semiconductor device comprising:
a semiconductor substrate comprising a first main surface and a second main surface opposite to said first main surface;
a first strain relief plate comprising a bottom surface which is in contact with said first main surface of said semiconductor substrate; and
a second strain relief plate comprising a top surface which is in contact with said second main surface of said semiconductor substrate,
wherein said semiconductor substrate includes:
a first semiconductor layer of a first conductivity type comprising a first bottom surface and a first top surface opposite to said first bottom surface, said first bottom surface forming said second main surface of said semiconductor substrate;
a second semiconductor layer of a second conductivity type comprising a second bottom surface and a second top surface opposite to said second bottom surface, said second bottom surface including an interface with said first top surface of said first semiconductor layer;
a third semiconductor layer of said first conductivity type comprising a third bottom surface and a third top surface opposite to said third bottom surface, said third bottom surface including an interface with said second top surface of said second semiconductor layer; and
a second main electrode which is formed on the whole of said first bottom surface of said first semiconductor layer and is in direct mechanical contact with said top surface of said second strain relief plate,
a plurality of protruding portions are arranged radially and circumferentially about said semiconductor substrate on said first main surface of said semiconductor substrate,
each of said plurality of protruding portions comprises a fourth semiconductor layer of said second conductivity type,
said fourth semiconductor layer comprises a fourth bottom surface and a fourth top surface opposite to said fourth bottom surface, said fourth bottom surface and a corresponding region out of said third top surface of said third semiconductor layer forming a pn junction,
said fourth top surface forms a top surface of a corresponding one out of said plurality of protruding portions;
said pn junction is located within said corresponding one of said plurality of said protruding portions,
a top surface of each of first protruding portions belonging to at least one group out of a first group of outermost protruding portions and a second group of innermost protruding portions is entirely covered with a first insulating layer, said outermost protruding portions located most outward in a radial direction out of said plurality of protruding portions, said innermost protruding portions located most inward in said radial direction out of said plurality of protruding portions,
a first clearance constantly exists between a top surface of said first insulating layer and a first region of said bottom surface of said first strain relief plate which is located immediately above said top surface of said first insulating layer,
a first main electrode is formed on a top surface of each of said plurality of protruding portions except said outermost protruding portions and said innermost protruding portions,
said first main electrode is in direct mechanical contact with said bottom surface of said first strain relief plate,
said first main surface of said semiconductor substrate includes an exposed surface of said fourth semiconductor layer for each of said plurality of protruding portions and exposed regions of said third top surface, and
a control electrode is formed as one pattern on a region of said first main surface in which no surface of said plurality of protruding portions is included.
2. The pressure contact type semiconductor device according to claim 1, wherein a top surface of each of second protruding portions belonging to the other group out of said first group and said second group is entirely covered with a second insulating layer, and
a second clearance constantly exists between a top surface of said second insulating layer and a second region of said bottom surface of said first strain relief plate which is located immediately above said top surface of said second insulating layer.
3. The pressure contact type semiconductor device according to claim 2,
wherein each of said outermost and innermost protruding portions is smaller in size than any other one of said plurality of protruding portions.
4. The pressure contact type semiconductor device according to claim 2,
wherein said outermost protruding portions are continuous with one another to form a single ring extending along an entire circumference of said semiconductor substrate.
5. A pressure contact type semiconductor device comprising:
a semiconductor substrate comprising a first main surface and a second main surface opposite to said first main surface;
a first strain relief plate comprising a bottom surface which is in contact with said first main surface of said semiconductor substrate; and
a second strain relief plate comprising top surface which is in contact with said second main surface of said semiconductor substrate,
wherein said semiconductor substrate includes:
a first semiconductor layer of a first conductivity type comprising a first bottom surface and a first top surface opposite to said first bottom surface, said first bottom surface forming said second main surface of said semiconductor substrate;
a second semiconductor layer of a second conductivity type comprising a second bottom surface and a second top surface opposite to said second bottom surface, said second bottom surface including an interface with said first top surface of said first semiconductor layer;
a third semiconductor layer of said first conductivity type comprising a third bottom surface and a third top surface opposite to said third bottom surface, said third bottom surface including an interface with said second top surface of said second semiconductor layer; and
a second main electrode which is formed on the whole of said first bottom surface of said first semiconductor layer and is in direct mechanical contact with said top surface of said second strain relief plate,
a plurality of protruding portions are arranged radially and circumferentially about said semiconductor substrate on said first main surface of said semiconductor substrate,
each of said plurality of protruding portions comprises a fourth semiconductor layer of said second conductivity type,
said fourth semiconductor layer comprises a fourth bottom surface and a fourth top surface opposite to said fourth bottom surface, said fourth bottom surface and a corresponding region out of said third top surface of said third semiconductor layer forming a pn junction,
said fourth top surface forms a top surface of a corresponding one out of said plurality of protruding portions;
said pn junction is located within said corresponding one of said plurality of said protruding portions,
a first main electrode is formed on a top surface of each of said plurality of protruding portions,
said first main electrode which is formed on a top surface of each of first protruding portions belonging to at least one group out of a first group of outermost protruding portions and a second group of innermost protruding portions, is constantly not in mechanical contact with said bottom surface of said first strain relief plate, said outermost protruding portions located most outward in a radial direction out of said plurality of protruding portions, said innermost protruding portions located most inward in said radial direction out of said plurality of protruding portions,
said first main electrode, which is formed on said top surface of each of said plurality of protruding portions, except said outermost and innermost protruding portions, is in direct mechanical contact with said bottom surface of said first strain relief plate,
said first main surface of said semiconductor substrate includes an exposed surface of said fourth semiconductor layer for each of said plurality of protruding portions and exposed regions of said third top surface, and
a control electrode is formed as one pattern on a region of said first main surface in which no surface of said plurality of protruding portions is included.
6. The pressure contact type semiconductor device according to claim 5,
wherein said first main electrode which is formed on a top surface of each of second protruding portions belonging to the other group out of said first and second groups is constantly not in contact with said bottom surface of said first strain relief plate.
7. The pressure contact type semiconductor device according to claim 6,
wherein said first strain relief plate is an annular member which comprises an inner peripheral surface and an outer peripheral surface,
said first strain relief plate includes:
a first missing portion provided in a first corner portion thereof at which said bottom surface, and said outer peripheral surface of said first strain relief plate meet each other; and
a second missing portion provided in a second corner portion thereof at which said bottom surface and said inner peripheral surface of said first strain relief plate meet each other,
a first clearance constantly exists between said first main electrode on each of said outermost protruding portions and said first missing portion located immediately above said first main electrode on each of said outermost protruding portions, and
a second clearance constantly exists between said first main electrode on each of said innermost protruding portions and said second missing portion located immediately above said first main electrode on each of said innermost protruding portions.