1. An integrated circuit, comprising:
a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal;
a first gated buffer configured to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal;
a second gated buffer configured to receive the first gated buffer output signal and configured to produce a second gated buffer output signal to be provided to a pin; and
a receive input buffer configured to be coupled to said pin and configured to receive an input signal from said pin;
wherein said integrated circuit operates in a test mode in which the second gated buffer is disabled thereby preventing a test signal provided to an input of the first mux from reaching the pin, the test signal provided instead through the first mux to the first gated buffer and to the receive buffer thereby testing at least the first mux.
2. The integrated circuit of claim 1 wherein, while in the test mode, a plurality of test signals are provided sequentially to the inputs of the first mux to test each of multiple channels in the first mux.
3. The integrated circuit of claim 1 further comprising a second mux configured to provide an enable signal to the first gated buffer, said second mux controlled during the test mode to enable the first gated buffer to control timing of the test signal to the receive input buffer.
4. The integrated circuit of claim 1 wherein, during said test mode, no signals are driven by the integrated circuit on the pin.
5. An integrated circuit, comprising:
a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal;
a gated buffer configured to receive the mux output signal from the first multiplexer and produce a gated buffer output signal;
a latch configured to receive the gated buffer output signal and configured to produce a latched output signal to be provided to a pin; and
a receive input buffer configured to be coupled to said pin and configured to receive an input signal from said pin;
wherein said integrated circuit operates in a test mode in which the latch is configured to latch the gated buffer output signal to be provided to said pin as an output signal from said pin while a test signal is provided to an input of the mux from reaching the pin, the test signal provided instead through the mux to the gated buffer and to the receive input buffer without the test signal being provided to said pin.
6. The integrated circuit of claim 5 further comprising a demultiplexer coupled to an output from said receive input buffer, said demultiplexer configured to demultiplex a signal from said receive buffer, wherein the test mode tests multiple channels of the first mux and the demultiplexer.
7. The integrated circuit of claim 5 further comprising a second mux whose output signal is an enable signal to the gated buffer.
8. A method of performing a loop back test on multiplexer logic in an integrated circuit, said multiplexer logic containing an multiplexer and coupled to an inputoutput pin for multiplexing data output signals to said pin, said method comprising;
causing an output latch to latch an output signal from a multiplexer to perpetuate said output signal from said multiplexer at the pin while internal loop back testing occurs;
performing an internal loop back test by providing a test signal to the multiplexer, looping the test signal from an output of the multiplexer back to a receive buffer, and comparing the looped back test signal to the provided test signal to check for an error; and
upon completion of the internal loop back test, causing a state of the output latch to change thereby to provide a data signal from said multiplexer to said pin.
9. The method of claim 8 further comprising not providing the test signal to the pin while performing the internal loop back test and instead driving the latch’s output signal on to the pin.
10. The method of claim 8 wherein the multiplexer comprises a plurality of inputs and wherein performing the internal loop back test comprises providing a test signal to each input of the multiplexer and comparing each such looped back test signal to each corresponding provided test signal to check for an error.
11. A method performing a loop back test on multiplexer logic in an integrated circuit, said multiplexer logic containing an multiplexer and coupled to an inputoutput pin for multiplexing data output signals to said pin, said method comprising:
causing an output gated buffer to prevent a signal from the multiplexer from reaching a pin;
providing a test signal to the multiplexer;
looping the test signal from an output of the multiplexer back to a receive input buffer;
comparing the looped back test signal to the provided test signal to check for an error; and
upon completion of a test, causing a state of the gated output buffer to change thereby to provide a data signal from said multiplexer to said pin.
12. The method of claim 11 wherein the multiplexer comprises a plurality of inputs and wherein providing the test signal to the multiplexer, looping the test signal, and comparing the looped back test signal to the provided test signal is repeated for each input of the multiplexer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid ejection head, comprising:
a substrate on a surface of which an energy-generating element for generating energy for ejecting liquid is formed; and
a flow path forming member formed on the substrate, the flow path forming member forming an ejection orifice for ejecting the liquid and a liquid flow path communicating with the ejection orifice, wherein
the flow path forming member includes, at a position surrounding the liquid flow path, first and second depressions that open to an upper surface of the flow path forming member and a groove that opens to the first depression, the ejection orifice opening to the second depression,
an angle between the upper surface of the flow path forming member and a slope surface of the first depression on the flow path forming member side is an obtuse angle, and
the groove has a serrated side wall.
2. A liquid ejection head according to claim 1, wherein the groove has a tapered shape in which an area of a cross-section thereof becomes smaller from the surface of the substrate toward the upper surface of the flow path forming member.
3. A liquid ejection head according to claim 1, wherein the ejection orifice has a tapered shape in which an area of a cross-section thereof becomes smaller from the surface of the substrate toward the upper surface of the flow path forming member.
4. A liquid ejection head, comprising:
a substrate on a surface of which an energy-generating element for generating energy for ejecting liquid is formed; and
a flow path forming member formed on the substrate, the flow path forming member forming an ejection orifice for ejecting the liquid and a liquid flow path communicating with the ejection orifice, wherein
the flow path forming member includes, at a position surrounding the liquid flow path, a depression that opens to an upper surface of the flow path forming member and a groove that opens to the depression,
an angle between the upper surface of the flow path forming member and a slope surface of the depression on the flow path forming member side is an obtuse angle,
the groove has a serrated side wall, and
the ejection orifice has a projection provided therein.
5. A liquid ejection head according to claim 4, wherein the groove has a tapered shape in which an area of a cross-section thereof becomes smaller from the surface of the substrate toward the upper surface of the flow path forming member.
6. A liquid ejection head according to claim 4, wherein the flow path forming member has a second depression which opens to the upper surface of the flow path forming member, and the ejection orifice opens to the second depression.
7. A liquid ejection head according to claim 6, wherein the ejection orifice has a tapered shape in which an area of a cross-section thereof becomes smaller from the surface of the substrate toward the upper surface of the flow path forming member.