1. A method of forming a semiconductor device comprising:
providing a substrate of a first conductivity type;
forming a gate stack structure overlying the substrate;
forming a drain region of a second conductivity type adjacent the gate stack structure, the second conductivity type being different from the first conductivity type, and wherein the drain region comprises a material having a smaller bandgap than a bandgap of the substrate; and
forming a source region of a second conductivity type adjacent the gate stack structure and on a side opposite that of the drain region, wherein the source region comprises a material having a larger bandgap than the bandgap of the substrate.
2. The method of claim 1, wherein the source region comprises a material different from a material of the drain region.
3. The method of claim 1, wherein forming the source region includes epitaxially growing the larger bandgap material.
4. The method of claim 1, wherein forming the source region includes implanting to form the larger bandgap material.
5. The method of claim 1, wherein the source region comprises carbon doped silicon (SiC).
6. The method of claim 1, wherein the drain region comprises silicon germanium (SiGe).
7. The method of claim 1, wherein the first conductivity type comprises p-type and the device comprises an NMOS non-volatile memory transistor.
8. The method of claim 1, wherein the first conductivity type comprises n-type and the device comprises a PMOS non-volatile memory transistor.
9. The method of claim 1, wherein the gate stack structure includes gate electrode overlying a charge storage layer.
10. The method of claim 1, wherein the gate stack structure includes a gate electrode overlying a top dielectric layer, the top dielectric layer overlying a charge storage layer, and the charge storage layer overlying a bottom dielectric layer.
11. The method of claim 1, wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a reading bias to the source region, a content of a charge storage layer of the non-volatile memory can be read with a minimal read disturb, the minimal read disturb corresponding to an occurrence of impact ionization insufficient to adversely affect the content of the charge storage layer.
12. The method of claim 1, wherein the larger bandgap material of the source region reduces an occurrence of impact ionization in the source region and substantially eliminates any low level charge injection to the gate stack structure that could undesirably affect a charge stored in a charge storage layer of the gate stack structure during a read operation with a biased source and grounded drain.
13. The method of claim 1, wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a programming bias to the source region, a content of a charge storage layer of the non-volatile memory can be programmed by means of hot carrier injection.
14. A semiconductor device comprising:
a substrate of a first conductivity type;
a gate stack structure overlying the substrate;
a drain region of a second conductivity type adjacent the gate stack structure, the second conductivity type being different from the first conductivity type, and wherein the drain region comprises a material having a smaller bandgap than a bandgap of the substrate; and
a source region of a second conductivity type adjacent the gate stack structure and on a side opposite that of the drain region, wherein the source region comprises a material having a larger bandgap than the bandgap of the substrate.
15. The device of claim 14, wherein the source region comprises a material different from a material of the drain region.
16. The device of claim 14, wherein the source region includes an epitaxially grown material.
17. The device of claim 14, wherein the source region includes a material with an implanted dopant.
18. The device of claim 14, wherein the source region comprises carbon doped silicon (SiC).
19. The device of claim 14, wherein the drain region comprises silicon germanium (SiGe).
20. The device of claim 14, wherein the first conductivity type comprises p-type and further wherein the device comprises an NMOS non-volatile memory transistor.
21. The device of claim 14, wherein the first conductivity type comprises n-type and further wherein the device comprises a PMOS non-volatile memory transistor.
22. The device of claim 14, wherein the gate stack structure includes gate electrode overlying a charge storage layer.
23. The device of claim 14, wherein the gate stack structure includes a gate electrode overlying a top dielectric layer, the top dielectric layer overlying a charge storage layer, and the charge storage layer overlying a bottom dielectric layer.
24. The device of claim 14, wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a reading bias to the source region, a content of a charge storage layer of the non-volatile memory can be read with a minimal read disturb, the minimal read disturb corresponding to an occurrence of impact ionization insufficient to adversely affect the content of the charge storage layer.
25. The device of claim 14, wherein the larger bandgap material of the source region reduces an occurrence of impact ionization in the source region and substantially eliminates any low level charge injection to the gate stack structure that could undesirably affect a charge stored in a charge storage layer of the gate stack structure.
26. The device of claim 14, wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a programming bias to the source region, a content of a charge storage layer of the non-volatile memory can be programmed by means of hot carrier injection.
27. The method of claim 1, wherein:
the step of forming the source is further characterized by the source comprising carbon doped silicon; and
the step of forming the drain is further characterized by the drain comprising germanium doped silicon.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pressure sensing left atrial occluding implantable medical device comprising:
a cardiac plug comprising an expandable lobe and an expandable disc proximal the lobe, wherein the expandable lobe is configured to expand into an anchoring arrangement within the left atrial appendage, and the expandable lobe is configured to expand into an occluding arrangement with the left atrial appendage; and
a MEMS coupled to the cardiac plug proximal of the disc, wherein the MEMS is configured to sense surrounding fluid pressure.
2. The device of claim 1, wherein the MEMS includes a CardioMEMS as manufactured by CardioMEMS, Inc.
3. The device of claim 1, wherein the cardiac plug includes an AMPLATZER\xae Cardiac Plug as manufactured by AGA Medical Corporation.
4. The device of claim 1, wherein the expandable lobe includes a Nitinol mesh.
5. The device of claim 1, wherein the device further includes a platform secured to the cardiac plug and on which the MEMS is secured.
6. The device of claim 5, wherein the platform includes titanium.
7. The device of claim 1, wherein the platform includes a distal threaded male member and a proximal threaded female member.
8. The device of claim 7, wherein the cardiac plug further comprises a proximal female threaded attachment that threadably couples with the distal threaded male member.
9. The device of claim 5, wherein the platform on which the MEMS is secured is permanently attached to the cardiac plug.
10. The device of claim 5, wherein the MEMS is secured to the platform via wires.
11. A system for sensing pressure in a left atrium near the confines of a left atrial appendage, the system comprising:
an anchor configured to achieve an anchoring interference fit within the confines of the left atrial appendage;
a MEMS coupled to the anchor and configured to protrude into the left atrium when the anchor has achieved the anchoring interference fit, wherein the MEMS is configured to sense surrounding fluid pressure; and
a telemetry device configured to wirelessly communicate with the MEMS to read fluid pressures sensed by the MEMS.
12. The system of claim 11, wherein the anchor is part of a cardiac plug.
13. The system of claim 12, wherein at least one of the MEMS includes a CardioMEMS as manufactured by CardioMEMS, Inc. or the cardiac plug includes an AMPLATZER\xae Cardiac Plug as manufactured by AGA Medical Corporation.
14. The system of claim 11, wherein the anchor includes an expandable lobe that is configured to achieve the anchoring interference fit.
15. The system of claim 14, wherein the lobe includes a Nitinol mesh.
16. A method of establishing a pressure sensing arrangement for sensing left atrial pressure, the method comprising:
creating an interference fit between an expandable anchor and a left atrial appendage; and
supporting a MEMS off of the anchor such that the MEMS is located in a volume of the left atrium, the MEMS being configured to sense surrounding fluid pressure.
17. The method of claim 16, wherein the MEMS and anchor are coupled together before being delivered together to the left atrial appendage.
18. The method of claim 16, wherein the MEMS is configured to wirelessly communicate with a telemetry wand.
19. The method of claim 16, wherein the anchor is part of a cardiac plug.
20. The method of claim 19, wherein at least one of the MEMS includes a CardioMEMS as manufactured by CardioMEMS, Inc. or the cardiac plug includes an AMPLATZER\xae Cardiac Plug as manufactured by AGA Medical Corporation.