1. A welding system, comprising:
a first welding torch having a consumable electrode;
a second welding torch having a non-consumable electrode;
a welding power supply connected to said first welding torch which outputs a pulsed welding waveform to melt said consumable electrode into a weld joint and generate a first arc between said consumable electrode and said weld joint, where said pulsed welding waveform has a plurality of peak current portions and a plurality of background current portions; and
a heat generation power supply connected to said second welding torch which outputs a pulsed heating signal to melt at least a portion of said weld joint and generate a second arc between said non-consumable electrode and said weld joint, where said pulsed heating signal has a plurality of peak current portions;
wherein at least one of said welding power supply and said heat generation power supply are controlled such that said pulsed heating signal is out-of-phase with said pulsed welding waveform such that no portion of each of said peak current portions of said pulsed heating signal occurs during said peak current portions of said pulsed welding waveform; and
wherein at least one of said pulsed welding waveform and said pulsed heating signal is an AC signal, and wherein at least one of said welding power supply and said heat generation power supply detects a short circuit between said electrode and said weld joint, and wherein upon detection of said short circuit said heat generation power supply controls said pulsed heating signal to create a short circuit clearing pulse having a peak current to clear said short circuit, and wherein said peak current of said short circuit clearing pulse ends prior to an end of a short circuit clearing pulse initiated by said welding power supply upon detection of said short circuit.
2. The welding system of claim 1, wherein each of said peak current portions of said pulsed heating signal is less in duration than each of said background current portions of said pulsed welding waveform.
3. The welding system of claim 1, wherein each of said pulsed heating signal and said pulsed welding waveform are AC.
4. A welding system, comprising:
a welding power supply which outputs a pulsed welding waveform to melt an electrode into a weld joint, where said pulsed welding waveform has a plurality of peak current portions and a plurality of background current portions; and
a heat generation power supply which outputs a pulsed heating signal to melt at least a portion of said weld joint, where said pulsed heating signal has a plurality of peak current portions;
wherein at least one of said welding power supply and said heat generation power supply are controlled such that said pulsed heating signal is out-of-phase with said pulse welding waveform such that at least a portion of each of said peak current portions of said pulsed heating signal does not occur during said peak current portions of said pulsed welding waveform,
wherein at least one of said welding power supply and said heat generation power supply detects a short circuit between said electrode and said weld joint, and wherein upon detection of said short circuit said heat generation power supply controls said pulsed heating signal to create a short circuit clearing pulse having a peak current to clear said short circuit, and
wherein said peak current of said short circuit clearing pulse ends prior to an end of a short circuit clearing pulse initiated by said welding power supply upon detection of said short circuit.
5. The welding system of claim 1, wherein said heat generation power supply is one of a TIG welding power supply or a plasma generation power supply.
6. The welding system of claim 1, wherein some of said peak current portions of said pulsed heating signal have a first polarity and the other of said peak current portions of said pulsed heating signal have a second polarity, and where said pulsed heating signal is controlled such that said peak current portions with said first polarity overlap at least a portion of each of said background current portions of said pulsed welding waveform.
7. The welding system of claim 1, wherein at least one of said welding power supply and said heat generation power supply are controlled such that said pulsed heating signal is out-of-phase with said pulse welding waveform by a phase angle in the range of 1 to 359 degrees, where said phase angle is measured between a beginning of said peak current portions of said pulsed welding waveform and a beginning of said peak current portions of said pulsed heating signal.
8. A method of welding, comprising:
providing first and second welding torches, where said first welding torch has a consumable electrode and said second welding torch has a non-consumable electrode;
providing a pulsed welding waveform to said consumable electrode to melt said consumable electrode into a weld joint and generate a first arc between said consumable electrode and said welding joint, where said pulsed welding waveform has a plurality of peak current portions and a plurality of background current portions;
providing a pulsed heating signal to melt at least a portion of said weld joint and generate a second arc between said non-consumable electrode and said weld joint, where said pulsed heating signal has a plurality of peak current portions; and
controlling at least one of said pulsed heating signal and said pulsed welding waveform such that no portion of each of said peak current portions of said pulsed heating signal occurs during said peak current portions of said pulsed welding waveform; and
wherein at least one of said pulsed welding waveform and said pulsed heating signal is an AC signal, detecting a short circuit between said electrode and said weld joint, and wherein upon detection of said short circuit creating a short circuit clearing pulse in said pulsed heating signal having a peak current to clear said short circuit; and initiating a short circuit clearing pulse in said pulsed welding waveform upon detection of said short circuit and wherein said peak current of said short circuit clearing pulse of said pulsed heating signal ends prior to an end of said short circuit clearing pulse in said pulsed welding waveform.
9. The welding method of claim 8, wherein each of said peak current portions of said pulsed heating signal is less in duration than each of said background current portions of said pulsed welding waveform.
10. The welding method of claim 8, wherein each of said pulsed heating signal and said pulsed welding waveform are AC.
11. A method of welding, comprising:
providing a pulsed welding waveform to an electrode to melt said electrode into a weld joint, where said pulsed welding waveform has a plurality of peak current portions and a plurality of background current portions;
providing a pulsed heating signal to melt at least a portion of said weld joint, where said pulsed heating signal has a plurality of peak current portions;
controlling at least one of said pulsed heating signal and said pulsed welding waveform such that at least a portion of each of said peak current portions of said pulsed heating signal does not occur during said peak current portions of said pulsed welding waveform;
detecting a short circuit between said electrode and said weld joint, and wherein upon detection of said short circuit creating a short circuit clearing pulse in said pulsed heating signal having a peak current to clear said short circuit; and
initiating a short circuit clearing pulse in said pulsed welding waveform upon detection of said short circuit and wherein said peak current of said short circuit clearing pulse of said pulsed heating signal ends prior to an end of said short circuit clearing pulse in said pulsed welding waveform.
12. The welding method of claim 8, further comprising creating said pulsed heating signal with one of a plasma power supply or a TIG welding power supply.
13. The welding method of claim 8, wherein some of said peak current portions of said pulsed heating signal have a first polarity and the other of said peak current portions of said pulsed heating signal have a second polarity, and where said pulsed heating signal is controlled such that said peak current portions with said first polarity overlap at least a portion of each of said background current portions of said pulsed welding waveform.
14. The welding method of claim 8, wherein said pulsed heating signal is out-of-phase with said pulse welding waveform by a phase angle in the range of 1 to 359 degrees, where said phase angle is measured between a beginning of said peak current portions of said pulsed welding waveform and a beginning of said peak current portions of said pulsed heating signal.
15. The welding system of claim 1, further comprising a controller coupled to the welding power supply and the heat generation power supply for controlling at least one of said welding power supply and said heat generation power supply such that said pulsed heating signal is out-of-phase with said pulse welding waveform such that at least a portion of each of said peak current portions of said pulsed heating signal does not occur during said peak current portions of said pulsed welding waveform.
16. The welding system of claim 15, wherein the second welding torch is a plasma torch.
17. The welding method of claim 8, further comprising a controller for controlling at least one of said pulsed heating signal and said pulsed welding waveform such that at least a portion of each of said peak current portions of said pulsed heating signal does not occur during said peak current portions of said pulsed welding waveform.
18. The welding method of claim 17, wherein said second welding torch is a plasma torch.
19. The welding system of claim 1, wherein said pulsed welding waveform is a DC signal and said pulsed heating signal is an AC signal.
20. The welding method of claim 8, wherein said pulsed welding waveform is a DC signal and said pulsed heating signal is an AC signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for automated test pattern generation (ATPG), the method comprising the step of generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test.
2. The method as claimed in claim 1, wherein the ATPG memory address locations comprise the same column in two rows of a column mux=\u201cm\u201d memory, where m\u22671.
3. The method as claimed in claim 2, wherein a memory cell at said column in one of said two row lines is programmed for program value \u20180\u2019 and a memory cell at said column in the other of said two row lines is programmed for program value \u20181\u2019.
4. The method as claimed in claim 3, wherein selecting between program value \u20180\u2019 and program value \u20181\u2019 is controlled by controlling precharge devices coupled to BLT and BLB of the respective memory cells.
5. The method as claimed in claim 4, wherein, where m>1, selecting between program value \u20180\u2019 and program value \u20181\u2019 is further controlled by controlling column mux devices coupled to BLT and BLB of the respective memory cells.
6. The method as claimed in claim 5, wherein logic levels of the column mux devices are controlled to be opposite to those of the precharge devices
7. The method as claimed in claim 1, wherein, when the memory is organized as column mux=\u201cm\u201d, where m>1, the ATPG memory address locations comprise different columns in a single row.
8. The method as claimed in claim 7, wherein a memory cell at one of said different columns is programmed for program value \u20180\u2019 and a memory cell at the other column is programmed for program value \u20181\u2019.
9. The method as claimed in claim 8, wherein selecting between program value \u20180\u2019 and program value \u20181\u2019 is controlled by controlling column mux devices and precharge devices coupled to BLT and BLB of the respective memory cells.
10. The method as claimed in claim 9, wherein a selection control of the precharge devices is an invert of a selection control of the columns mux devices.
11. The method as claimed in claim 1, comprising disabling a row decoder of the memory and using an ATPG world line generator for selecting the ATPG memory address locations.
12. The method as claimed in claim 1, comprising providing voltage differentials associated with respective ATPG memory address locations to a sense amplifier of the memory for output into the logic under test.
13. A system for automated test pattern generation (ATPG), the system comprising means for generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test.
14. The system as claimed in claim 13, wherein the ATPG memory address locations comprise the same column in two row of a column mux=\u201cm\u201d memory, where m\u22671.
15. The system as claimed in claim 14, wherein a memory cell at said column in one of said two row lines is programmed for program value \u20180\u2019 and a memory cell at said column in the other of said two row lines is programmed for program value \u20181\u2019.
16. The system as claimed in claim 15, wherein a means for selecting between program value \u20180\u2019 and program value \u20181\u2019 is configured to control precharge devices coupled to BLT and BLB of the respective memory cells.
17. The system as claimed in claim 16, wherein, where m>1, the means for selecting between program value \u20180\u2019 and program value \u20181\u2019 is further configured to control column mux devices coupled to BLT and BLB of the respective memory cells.
18. The system as claimed in claim 17, wherein the means for selecting is configured such that logic levels of the column mux devices are controlled to be opposite to those of the precharge devices
19. The system as claimed in claim 13, wherein, when the memory is organized as column mux=\u201cm\u201d, where m>1, the ATPG memory address locations comprise different columns in a single row.
20. The system as claimed in claim 19, wherein a memory cell at one of said different columns is programmed for program value \u20180\u2019 and a memory cell at the other column is programmed for program value \u20181\u2019.
21. The system as claimed in claim 10, wherein a means for selecting between program value \u20180\u2019 and program value \u20181\u2019 is configured to control column mux devices and precharge devices coupled to BLT and BLB of the respective memory cells.
22. The system as claimed in claim 21, wherein the means for selecting is configured such that a selection control of the precharge devices is an inverse of a selection control of the columns mux devices.
23. The system as claimed in claim 13, further comprising means for disabling a Rowdecoder of the memory and using an ATPG world line generator for selecting the ATPG memory address locations.
24. The system as claimed in claim 13, further comprising a sense amplifier of the memory, wherein the sense amplifier is configured to receive voltage differentials associated with respective ATPG memory address locations for output into the logic under test.
25. A memory configured for automated test pattern generation (ATPG), the memory comprising ATPG memory address locations for generating a test pattern for ATPG as claimed in claim 1.
26. A memory, comprising:
a first test memory cell;
a data-storage memory cell; and
a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
27. The memory of claim 26 wherein the first test memory cell is configured to store a logic one.
28. The memory of claim 26 wherein the first test memory cell is configured to store a logic zero.
29. The memory of claim 26, further including:
a test row;
a data row;
wherein the test memory cell is located in the test row; and
wherein the data memory cell is located in the data row.
30. The memory of claim 26, further including:
a test row;
a data row;
wherein the first test memory cell is located in the test row and is configured to store a logic value;
wherein the data-storage memory cell is located in the data row;
a second test memory cell located in the test row and configured to store a logic value different than the logic value stored in the first test memory cell; and
wherein the test circuit is configured to enable the second test memory cell during the test mode.
31. The memory of claim 26, further comprising:
a sense amplifier;
a bit line coupled to the first test memory cell;
a precharger configured to couple the bit line to a precharge voltage level in response to the test circuit; and
a selector configured to couple the sense amplifier to the bit line in response to the test circuit.
32. The memory of claim 26, further comprising:
wherein the test circuit is operable to generate a control signal;
a sense amplifier;
a bit line coupled to the first test memory cell;
a precharger configured to couple the bit line to a precharge voltage level in response to a signal derived from the control signal; and
a selector configured to couple the sense amplifier to the bit line in response to an inverse of the signal derived from the control signal.
33. The memory of claim 26, further including:
a test column;
wherein the first test memory cell is located in the test column and is configured to store a logic value;
a second test memory cell located in the test column and configured to store a logic value different than the logic value stored in the first test memory cell; and
wherein the test circuit is configured to enable the second test memory cell during the test mode.
34. The memory of claim 26, further including:
first and second test rows;
wherein the first test memory cell is located in the first test row and is configured to store a logic value;
a second test memory cell located in the second test row and configured to store a logic value different than the logic value stored in the first test memory cell; and
wherein the test circuit is configured to enable the second test memory cell during the test mode.
35. The memory of claim 26, further including:
first and second test rows;
a test column;
wherein the first test memory cell is located in the first test row and in the test column and is configured to store a logic value;
a second test memory cell located in the second test row and in the test column and configured to store a logic value different than the logic value stored in the first test memory cell; and
wherein the test circuit is configured to enable the second test memory cell during the test mode.
36. The memory of claim 26, further comprising:
first and second bit lines coupled to the first test memory cell;
a first precharger configured to couple the first bit line to a precharge voltage level in response to first control signal from the test circuit; and
a second precharger configured to couple the second bit line to the precharge voltage level in response to second control signal from the test circuit.
37. An integrated circuit, comprising:
a first test memory cell;
a data-storage memory cell; and
a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
38. A system, comprising:
a first integrated circuit, including:
a first test memory cell;
a data-storage memory cell; and
a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode; and
a second integrated circuit coupled to the first integrated circuit.
39. The system of claim 38 wherein the first and second integrated circuits are disposed on a same die.
40. The system of claim 38 wherein the first and second integrated circuits are disposed on respective dies.
41. The system of claim 38 wherein one of the first and second integrated circuits includes a controller.
42. A method, comprising:
activating a first test memory cell during a test mode; and
deactivating a data-storage memory cell during the test mode.
43. The method of claim 42, further including:
allowing the first test memory cell to change a signal on a bit line from a first logic level to a second logic level; and
coupling the bit line to a sense amplifier after the signal on the bit line has the second logic level.
44. The method of claim 42, further including:
allowing the first test memory cell to change a signal on a bit line from a precharge logic level to another logic level; and
coupling the bit line to a sense amplifier after the signal on the bit line has the other logic level.
45. The method of claim 42, further including:
allowing the first test memory cell to change a signal on a bit line from a high logic level to a low logic level; and
coupling the bit line to a sense amplifier after the signal on the bit line has the low logic level.
46. The method of claim 42 wherein activating the first test memory cell includes activating a row including the first test memory cell.
47. The method of claim 42 wherein activating the first test memory cell includes activating a column including the first test memory cell.
48. The method of claim 42 wherein activating the first test memory cell includes activating a column including the first test memory cell and the data-storage memory cell.
49. The method of claim 42, further including configuring the first test memory cell to permanently store a logic one.
50. The method of claim 42, further including configuring the first test memory cell to permanently store a logic zero.
51. The method of claim 42, further including:
coupling a precharge signal to a first bit line coupled to the first test memory cell; and
uncoupling the precharge signal to a second bit line coupled to the first test memory cell.
52. The method of claim 42, further including:
wherein the first test memory cell stores a first logic level;
coupling the first test memory cell to an output node;
uncoupling the first test memory cell from the output node;
activating a second test memory cell that stores a second logic level; and
coupling the second test memory cell to the output node.
53. The method of claim 42, further including:
wherein the first test memory cell stores a first logic level;
coupling the first test memory cell to an output node;
deactivating the first test memory cell;
activating a second test memory cell that stores a second logic level; and
coupling the second test memory cell to the output node.
54. The method of claim 42, further including:
wherein the first test memory cell stores a first logic level;
activating a second test memory cell that stores a second logic level such that the first and second test memory cells are simultaneously active;
coupling the first test memory cell to an output node;
uncoupling the first test memory cell from the output node; and
coupling the second test memory cell to the output node.