1. A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising:
a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths based on a strength of a control signal;
a first control loop controlling said strength of said control signal to cause synchronization of edges of said reference signal with edges of the output of a last one of said first plurality of delay elements, said first control loop containing said first plurality of delay elements; and
a second control loop also controlling said strength of said control signal to avoid synchronization of edges of the output of the last one of said plurality of delay elements with edges separated by multiple time periods of said reference signal, wherein said second control loop comprises a second plurality of delay elements generating a corresponding plurality of dummy signals, and wherein the plurality of delayed signals pass through at least some of the first plurality of delay elements and wherein the plurality of delayed signals do not pass through the second plurality of delay elements.
2. A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising:
a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths based on a strength of a control signal;
a first control loop controlling said strength of said control signal to cause synchronization of edges of said reference signal with edges of the output of a last one of
said first plurality of delay elements, said first control loop containing said first plurality of delay elements; and
a second control loop also controlling said strength of said control signal to avoid situations of synchronization of edges of the output of the last one of said plurality of delay elements with edges separated by multiple time periods of said reference signal;
wherein said second control loop comprises a second plurality of delay elements generating a corresponding plurality of dummy signals, wherein said plurality of delayed signals do not pass through the second plurality of delay elements; and
wherein said second control loop performs said avoiding by determining situations in which a total delay caused by said first plurality of delay elements has crossed an upper threshold.
3. The DLL circuit of claim 2, wherein said upper threshold equals 1.3 times a time period of said reference signal.
4. The DLL circuit of claim 3, wherein said second control loop also checks whether said total delay is lower than a lower threshold and control said strength to cause said total delay to further increase.
5. The DLL circuit of claim 4, wherein said lower threshold equals 0.7 times of said time period of said reference signal.
6. The DLL circuit of claim 5, wherein said determining and said checking are performed by examining said plurality of dummy signals.
7. A delay locked loop (DLL) circuit generating a plurality of delayed signals from a reference signal, each of said plurality of delayed signals being delayed by a corresponding different delay magnitude in comparison to said reference signal, said DLL circuit comprising:
a first plurality of delay elements connected in series, said first plurality of delay elements receiving said reference signal and generating said plurality of delayed signals on corresponding first plurality of output paths;
a duty cycle correction circuit generating a modified signal from said reference signal, said modified signal having a duty cycle different from the duty cycle of said reference signal if the duty cycle of said reference signal is not close to 50%;
a phase detector comparing a phase of said reference signal and the delayed signal on an output path of a last one of said first plurality of delay elements, and controlling a magnitude of delay caused by each of said first plurality of delay elements at least until edges of said reference signal and the delayed signal are synchronized;
a second plurality of delay elements also connected in series and receiving said modified signal, said second plurality of delay elements generating a plurality of dummy signals on corresponding second plurality of output paths, wherein a signal path between the reference signal and the delayed signal on said output path does not pass through the second plurality of delay elements; and
a lock detector determining whether a total delay caused by said first plurality of delay elements is more than an upper threshold by examining at least some of said plurality of dummy signals, said lock detector causing said magnitude of said delay to be further decreased if said total delay is more than said upper threshold even if said phase detector otherwise determines that said edges of said reference signal and the delayed signal are synchronized.
8. The DLL circuit of claim 7, wherein said lock detector determines whether said total delay caused by said first plurality of delay elements is less than a lower threshold by examining said plurality of dummy signals, and causes said first plurality of delay elements to increase said total delay.
9. The DLL circuit of claim 7, wherein said first plurality of delay elements and said second plurality of delay elements receive a same reference voltage which controls the corresponding delay caused.
10. The DLL circuit of claim 9, further comprising:
a capacitor which provides said same reference voltage;
a first charge pump charging said capacitor under the control of said phase detector to control said magnitude of delay;
a second charge pump charging said capacitor under the control of said lock detector to also control said magnitude of delay.
11. The DLL circuit of claim 10, wherein said second charge pump operates to control said magnitude of delay only until said total delay is more than said upper threshold.
12. The DLL circuit of claim 10, wherein each of said first plurality of delay elements introduces equal delay such that Qth one of said plurality of delayed signals is delayed by (Q*TX), wherein T represents the total time period of said reference signal and X represents the total number of said first plurality of delay elements.
13. The DLL circuit of claim 10, wherein said phase detector causes positive edges of said reference signal to be synchronized with positive edges of the output of said last one of said first plurality of elements.
14. The DLL circuit of claim 10, wherein said upper threshold equals 1.3 times said time period of said reference signal and said lower threshold equals 0.7 times said time period of said reference signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A network-based hardwaresoftware system for accessing, obtaining, and aggregating disparately sourced message data on behalf of requesting users comprising:
a first server connected to the network for accessing targeted HTTP sourced message data on behalf of the users;
a second server connected to network for accessing targeted voice message data on behalf of the users;
a data normalizing software application for receiving data obtained by the first and second servers and for normalizing the data into a common machine-readable language; and
a data repository accessible from first and second servers and from the data normalizing application, the data repository for storing data about the users, data about accessible data sources, and data aggregated for the users;
characterized in that a user subscribing to the system receives voice messaging reconstructed from the normalized data, the normalized data comprising aggregated voice-based and text-based messages originally obtained from the disparate data sources.
2. The system of claim 1 hosted on the Internet network.
3. The system of claim 1, wherein an XML parser is utilized by the first server for parsing the HTTP-sourced data messages for the target data.
4. The system of claim 3, wherein the XML parser is capable of parsing at least HTML, WML, HDML, CHTMLI-Mode and SGML.
5. The system of claim l,wherein the voice data messages accessed by the second server include at least IVR-driven messages hosted by third-party services and voice messages available from voice browser systems running voice XML software.
6. The system of claim 1, wherein the data repository houses the data normalizing software application.
7. The system of claim 1, wherein the data normalizing application includes a data dissemination engine for reading parsed data before normalization.
8. The system of claim 7, wherein the data is normalized into voice XML that is reconstructed into voice using server-side speech objects.
9. The system of claim 1, further comprising:
a computer telephony server connected to the network for interfacing with subscribing clients and for reconstructing voice XML into audible speech that is rendered to requesting users;
characterized in that the computer telephony server uses text-to-speech software and voice browser software to construct synthesized speech from the normalized data and render it to users over a telephony or Web-based interface.
10. The system of claim 9, wherein the computer telephony server is capable of outbound dialing and accepting incoming calls.
11. The system of claim 10, wherein outbound dialing capabilities include dialing into at least a public switched telephone network and into a wireless cellular network.
12. The system of claim 9 accessible from at least one of a POTS telephone, a cellular telephone, and a mobile computing device operating in wireless mode.
13. A voice-message gathering server connected to a data packet network, the gathering server for gathering voice data from disparate data sources on behalf of users comprising:
a computer telephony interface and software for dialing and connecting to telephony numbers and for excepting telephony calls;
an instance of sound recorder software for recording voice messages;
an instance of voice-based navigation software for interacting with Web-based voice data sources; and
an instance of interactive voice-response-software for interacting with telephony-based voice data sources;
characterized in that upon access and connection to a voice data source, the gathering server leverages a requesting users authentication credentials and recorded voice credentials if required for the purpose of accessing and then recording voice messages on behalf of the user.
14. The voice-message gathering server of claim 13, wherein the data-packet-network is the Internet network.
15. The voice-message gathering server of claim 13, wherein the voice messages are digital voice files.
16. The voice-message gathering server of claim 13, wherein the voice messages are analog voice recordings.
17. A method for normalizing message data gathered from disparate data sources on behalf of a requesting user and reconstructing the normalized data into audible voice data for presentation over a network including connected networks to a user interface comprising steps of:
(a) disseminating the gathered data and converting the data into a common machine readable language;
(b) aggregating the normalized data into a common database;
(c) accessing the normalized data from the database according to user instruction;
(d) reconstructing the normalized data into synthesized speech;
(e) establishing a communications link to the user for the purpose of data transfer; and
(f) rendering the reconstructed voice messaging to the user over the communication link.
18. The method of claim 17 wherein some of the data sources are hosted on the Internet network and some of the data sources are accessible through a telephony network.
19. The method of claim 17 wherein in step (a), some of the data is recorded voice data and some of the data is text data.
20. The method of claim 17 wherein in step (a), the common language is XML-based.
21. The method of claim 17 wherein in step (b), the normalized XML files contain references to speech objects within accompanying DTDs.
22. The method of claim 17 wherein in step (d), the synthesized speech is of the form of digital speech.
23. The method of claim 17 wherein in step (e), the communications link includes a wireless cellular link established through a wireless network gateway connected to the Internet network.
24. The method of claim 17 wherein in step (e), the communications link includes a wired telephony link established through a telephony-network bridge connected to the Internet network.
25. The method of claim 17 wherein in step (f), the user receives the voice messaging in the form of a digital voice file at the user end.
26. The method of claim 17 wherein in step (f), the user receives the voice messaging in the form of an analog recording at the user end.
27. The method of claim 17 wherein steps (b) and (c) are omitted in the case of a real-time user request of an established and existing communication link.