1. A system configured to interact with a virtual bus interface that is configured to produce a bus-type transaction from a point-to-point type transaction, the system comprising:
a detection logic configured to detect whether the point-to-point transaction to be processed by the virtual bus interface includes a data-type field that stores a data from which a value for a header-type field in a bus-type transaction can be produced; and
a decode logic operably connected to the detection logic, the decode logic being configured to extract the data from the data-type field, to process the data into the value, and to selectively store the value in the header-type field in the bus-type transaction.
2. The system of claim 1, where the detection logic detects whether the point-to-point transaction includes a data-type field that stores a data from which a value for a header-type field can be produced by examining a transaction type associated with the point-to-point transaction.
3. The system of claim 1, where the decode logic extracts the data from the data-type field in a bit-field wise manner.
4. The system of claim 3, where upon detecting that a point-to-point transaction stores a data from which a value for a header-type field can be produced, the detection logic generates a signal that is distributed to one or more of the decode logic and the virtual bus interface.
5. The system of claim 1, where the bus-type transaction comprises a front-side bus transaction.
6. A virtual bus interface system, comprising:
a point-to-point transaction logic configured to receive a packet associated with a point-to-point transaction;
a bus-type transaction logic operably connected to the point-to-point transaction logic, the bus-type transaction logic being configured to produce a bus-type transaction corresponding to the point-to-point transaction from the packet associated with the point-to-point transaction;
a detection logic operably connected to the point-to-point transaction logic, the detection logic being configured to detect whether the packet associated with the point-to-point transaction includes a data flit that encodes a non-memory-data value; and
a decode logic operably connected to the detection logic and the bus-type transaction logic, the decode logic being configured to extract the non-memory-data value from the data flit, to decode the non-memory data value, and to selectively provide the decoded non-memory-data value to the bus-type transaction logic.
7. The system of claim 6, where the detection logic detects whether the packet associated with point-to-point transaction includes a data flit that encodes a non-memory-data value by examining a transaction type associated with the point-to-point transaction.
8. The system of claim 7, where the decode logic extracts the non-memory-data value from the data flit in a bit-field wise manner.
9. The system of claim 6, where upon detecting that that packet associated with the point-to-point transaction includes a data flit that encodes a non-memory-data value, the detection logic generates a signal that is distributed to one or more of, the point-to-point transaction logic, the bus-type transaction logic, and the decode logic.
10. The system of claim 6, where the virtual bus interface produces a bus transaction for a front-side bus.
11. A computer configured with a virtual bus interface system, the virtual bus interface system comprising:
a point-to-point transaction logic configured to receive a packet associated with a point-to-point transaction;
a bus-type transaction logic operably connected to the point-to-point transaction logic, the bus-type transaction logic being configured to produce a bus-type transaction corresponding to the point-to-point transaction from the packet associated with the point-to-point transaction;
a detection logic operably connected to the point-to-point transaction logic, the detection logic being configured to determine whether the packet associated with the point-to-point transaction includes a data flit that encodes a non-memory-data value; and
a decode logic operably connected to the detection logic and the bus-type transaction logic, the decode logic being configured to extract the non-memory-data value from the data flit, to decode the non-memory data value, and to selectively provide the decoded non-memory-data value to the bus-type transaction logic.
12. A method, comprising:
in a virtual bus interface, detecting a completion event associated with receiving a point-to-point transaction to be processed into a bus-type transaction by the virtual bus interface;
determining whether the point-to-point transaction includes a data flit that stores a value to be processed into a header-type field in the bus-type transaction, and
upon determining that a data flit stores a value to be processed into a header-type field in the bus-type transaction:
selectively extracting the value from the data flit; and
producing a header-type value from the extracted value.
13. The method of claim 12, where determining whether the point-to-point transaction includes a data flit that stores a value to be processed into a header-type field includes examining a transaction type associated with the point-to-point transaction.
14. The method of claim 13, where the value is extracted in a bit-field wise manner from the data flit.
15. The method of claim 14, including:
establishing a decode function for a point-to-point transaction type in which a data flit encodes a non-memory data value; and
upon determining that a data flit encodes a non-memory data value, passing the data flit to an established decode function.
16. A computer-readable medium storing processor executable instructions operable to perform a method, the method comprising:
in a virtual bus interface, establishing a decode function for a point-to-point transaction type in which a data flit encodes a non-memory data value;
detecting a completion event associated with receiving a point-to-point transaction to be processed into a bus-type transaction by the virtual bus interface;
determining whether the point-to-point transaction includes a data flit that stores a value to be processed into a header-type field in the bus-type transaction by examining a transaction type associated with the point-to-point transaction;
upon determining that a data flit stores a value to be processed into a header-type field in the bus-type transaction, passing the data flit to an established decode function, and storing a decoded value returned from the decode function.
17. A system, comprising:
means for determining whether a point-to-point transaction available to a virtual bus interface includes a data flit that stores non-memory-data information that will be stored in a bus-type header-type field;
means for bitwise field extracting the non-memory-data information from the data flit; and
means for decoding the extracted non-memory-data information and making the decoded non-memory-data information available to a virtual bus interface logic configured to produce a header-type field for a bus-type transaction.
18. A set of application programming interfaces embodied on a computer-readable medium for execution by a computer component in conjunction with producing a header-type field for a bus-type transaction from non-memory-data information stored in a data flit in a point-to-point type transaction, comprising:
a first interface for communicating the data flit that encodes the non-memory-data information;
a second interface for communicating a non-memory-data value extracted from the data flit; and
a third interface for communicating a header-type data value for the bus-type transaction, where the header-type data value is produced from the non-memory-data value extracted from the data flit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a variable resistance memory device, comprising:
forming a first electrode;
forming a first metal oxide layer which satisfies chemical stoichiometry, over the first electrode;
forming a second metal oxide layer which is lower in oxygen content than the first metal oxide layer by reducing a part of the first metal oxide layer; and
forming a second electrode over the second metal oxide layer.
2. The method of claim 1, wherein the forming of the first metal oxide layer is performed through an atomic layer deposition (ALD) or a chemical vapor deposition (CVD).
3. The method of claim 1, wherein the forming of the second metal oxide layer is performed using plasma processing under an atmosphere of a reduction gas.
4. The method of claim 3, wherein the reduction gas include at least one of H2 and NH3.
5. The method of claim 1, wherein the first metal oxide layer includes Ta2O5, and the second metal oxide layer includes TaOx, x being less than 2.5.
6. The method of claim 1, wherein the second metal oxide layer has a thickness larger than the first metal oxide layer.
7. The method of claim 3, wherein relative thicknesses of the first metal oxide layer and the second metal oxide layer are controlled by adjusting a time of the plasma processing.
8. The method of claim 1, further comprising:
forming a material layer having an energy band gap larger than the first metal oxide layer, over the first electrode, before the forming of the first metal oxide layer.
9. The method of claim 1, further comprising:
forming a material layer having an energy band gap larger than the first metal oxide layer, over the second metal oxide layer, before the forming of the second electrode.
10. The method of claim 1, further comprising:
forming a third metal oxide layer for supplying oxygen vacancy to the second metal oxide layer, over the second metal oxide layer, before the forming of the second electrode.
11. The method of claim 1, wherein the forming of the second metal oxide layer comprises replacing oxygen of the part of the first metal oxide layer with oxygen vacancy.
12. A method for fabricating a variable resistance memory device, comprising:
alternately stacking a plurality of first material layers and a plurality of interlayer dielectric layers, over a substrate;
forming a hole which exposes sidewalls of the plurality of first material layers by selectively etching the alternately stacked structure;
forming a first metal oxide layer which satisfies chemical stoichiometry, in the hole;
forming a second metal oxide layer which is lower in oxygen content than the first metal oxide layer by reducing a part of the first metal oxide layer; and
forming a second electrode in the hole in which the second metal oxide layer is formed.
13. The method of claim 12, wherein the forming of the first metal oxide layer is performed through an atomic layer deposition (ALD) or a chemical vapor deposition (CVD).
14. The method of claim 12, wherein the forming of the second metal oxide layer is performed using plasma processing under an atmosphere of a reduction gas.
15. The method of claim 12, wherein the first metal oxide layer includes Ta2O5, and the second metal oxide layer includes TaOx, x being less than 2.5.
16. The method of claim 12, wherein the second metal oxide layer has a thickness larger than the first metal oxide layer.
17. The method of claim 14, wherein relative thicknesses of the first metal oxide layer and the second metal oxide layer are controlled by adjusting a time of the plasma processing.
18. The method of claim 12, further comprising:
forming a second material layer having an energy band gap larger than the first metal oxide layer, in the hole, before the forming of the first metal oxide layer.
19. The method of claim 12, further comprising:
forming a second material layer having an energy band gap larger than the first metal oxide layer, on the second metal oxide layer, before the forming of the second electrode.
20. The method of claim 12, further comprising:
forming a third metal oxide layer for supplying oxygen vacancy to the second metal oxide layer, on the second metal oxide layer, before the forming of the second electrode.
21. The method of claim 12, wherein the first material layers comprise conductive layers.
22. The method of claim 12, further comprises:
replacing the first material layers with conductive layers, after the forming of the second electrode,
wherein the first material layers comprise sacrificial layers which have an etching selectivity with respect to the interlayer dielectric layers.
23. The method of claim 12, wherein the forming of the second metal oxide layer comprises replacing oxygen of the part of the first metal oxide layer with oxygen vacancy.
24. A variable resistance memory device comprising:
a bottom electrode;
a variable resistance material layer including a first metal oxide layer and a second metal oxide layer which are sequentially stacked over the bottom electrode, wherein the first metal oxide satisfies chemical stoichiometry, and the second metal oxide layer is lower in oxygen content than the first metal oxide layer while having the same material as the first metal oxide layer; and
a top electrode formed over the variable resistance material layer.
25. The variable resistance memory device of claim 24, the first metal oxide layer includes a Ta2O5 layer and the second metal oxide layer includes a TaOx layer, x being less than 2.5.
26. The variable resistance memory device of claim 24, further comprising:
a material layer interposed between the bottom electrode and the variable resistance material layer or between the top electrode and the variable resistance material layer and having an energy band gap larger than the first metal oxide layer.
27. The variable resistance memory device of claim 24, further comprising:
a third metal oxide layer interposed between the top electrode and the variable resistance material layer and configured to supply oxygen vacancy to the second metal oxide layer.
28. The variable resistance memory device of claim 24, wherein the second metal oxide layer has a thickness larger than the first metal oxide layer.
29. The variable resistance memory device of claim 24, wherein the second metal oxide layer includes more oxygen vacancy than the first metal oxide layer.