1. A leash assembly for a pet, comprising:
a leash unit including
a handle portion that is formed into a loop and that has opposite ends,
a straight portion that is generally straight in shape, and that has a first end connected to one of said opposite ends of said handle portion, and a second end opposite to said first end thereof, and
a coiled portion that is helical in shape, and that has a first end connected to the other of said opposite ends of said handle portion, and a second end opposite to said first end thereof; and
first and second clips, each of which is provided on said second end of a respective one of said straight portion and said coiled portion of said leash unit.
2. The leash assembly as claimed in claim 1, wherein said leash unit is in the form of a single piece.
3. The leash assembly as claimed in claim 1, further comprising a fastening member that interconnects said opposite ends of said handle portion of said leash unit.
4. The leash assembly as claimed in claim 1, further comprising a tubular handgrip sleeved on said handle portion of said leash unit.
5. The leash assembly as claimed in claim 1, wherein said second end of said straight portion of said leash unit passes through said first clip, said leash assembly further comprising a fastening member for forming said second end of said straight portion of said leash unit into a loop.
6. The leash assembly as claimed in claim 1, wherein said second end of said coiled portion of said leash unit passes through said second clip, said leash assembly further comprising a fastening member for forming said second end of said coiled portion of said leash unit into a loop.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A process for fabricating a DRAM, suitable for a substrate on which a plurality of word lines and a plurality of sourcedrain regions on sides of each of these word lines are formed, the process comprising:
forming a plurality of bit line contacts and a plurality of node contacts in electric contact with the sourcedrain regions;
forming a first patterned insulating layer on the substrate, in which a plurality of openings is formed in the insulating layer to expose the bit line contacts;
covering a first conductive layer and a second insulating layer in sequence on the substrate to electrically connect the first conductive layer to the bit line contacts;
patterning the second insulating layer, the first conductive layer and the first insulating layer in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connected to the bit line contacts, thereby exposing the node contacts, wherein the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines;
forming a plurality of spacers on sidewalls of the bit line stacked structure;
forming a plurality of second conductive layers conformal to surfaces of the trenches; and
patterning the second conductive layers to form a plurality of bottom electrodes connected to the node contacts.
2. The process of claim 1, wherein the first conductive layer consists of a polysilicon layer and a metal silicide layer thereon.
3. The process of claim 2, wherein the depth of the trench between the bit line stacked structures is adjusted by changing the thickness of the metal silicide layer, thereby adjusting resistance of the bit line.
4. The process of claim 2, wherein the depth of the trench between the bit line stacked structures is adjusted by changing the thickness of the metal silicide layer, thereby adjusting a surface area of the bottom electrode.
5. The process of claim 1, wherein forming the bit line contacts and the node contacts further comprises:
covering the substrate with an insulating layer;
performing a self-aligned contact process to form a plurality of bit line contact openings and a plurality of node contact openings in the insulating layer, thereby exposing the sourcedrain regions; and
filling the self-aligned bit line contact openings and the self-aligned node contact openings with a first conductive material.
6. The process of claim 5, wherein the insulating layer is made of silicon oxide.
7. The process of claim 1, wherein forming the second conductive layers on the surfaces of the trenches further comprises:
forming a second conductive material conformal to the substrate;
filling a plurality of photoresist layers in the trenches;
removing the second conductive material outside the trenches by etching back or chemical mechanic polishing; and
removing the photoresist layers.
8. The process of claim 1, wherein each of the second conductive layers is an amorphous silicon layer or a polysilicon layer having a hemispherical grained silicon layer thereon.
9. The process of claim 1, wherein each of the second conductive layers is an amorphous silicon layer, the process further comprising forming a hemispherical grained silicon layer on the bottom electrode of amorphous silicon.
10. The process of claim 1, wherein the first insulating layer is made of silicon oxide.
11. The process of claim 1, wherein the second insulating layer is made of silicon oxide.
12. The process of claim 1, wherein the spacer is made of silicon nitride.
13. A structure of a DRAM, suitable for formation on a substrate, comprising:
a plurality of word lines located on the substrate;
a plurality of sourcedrain regions disposed on sides of each of the word lines;
a first insulating layer located on the word line, the sourcedrain region and the substrate;
a plurality of bit line contacts and a plurality of node contacts, in which the bit line contacts and the node contacts are located in the first insulating layer and are in electric contact with the sourcedrain regions;
a plurality of bit line stacked structures located on the bit line contacts and the first insulating layer, in which the bit line stacked structures are orthogonal to the word lines, and each of the bit line stacked structures is built up by stacking a second insulating layer, a bit line and a third insulating layer from bottom to top, with the bit line passing through the second insulating layer and electrically connecting to the bit line contacts;
a plurality of spacers located on sidewalls of the bit line stacked structures and forming a plurality of trenches; and
a plurality of bottom electrodes located on surfaces of the trenches between the spacers, each bottom electrode being electrically connected to one of the node contacts.
14. The structure of claim 13, wherein the first conductive layer comprises a polysilicon layer and a metal silicide layer thereon.
15. The structure of claim 13, wherein the bottom electrode is made of polysilicon, and a hemispherical grained silicon layer is formed on a surface of each of the bottom electrodes.
16. The structure of claim 13, wherein the bottom electrode is made of amorphous silicon, and a hemispherical grained silicon layer is formed on a surface of each of the bottom electrodes.
17. The structure of claim 13, wherein the first insulating layer is made of silicon oxide.
18. The structure of claim 13, wherein the second insulating layer is made of silicon oxide.
19. The structure of claim 13, wherein the third insulating layer is made of silicon oxide.
20. The structure of claim 13, wherein the spacers is made of silicon nitride.