1. A cryptographic apparatus, comprising:
a plurality of cryptographic processing circuits, each of which includes a flag storage unit that stores therein a CipherText Stealing (CTS) flag indicating whether an encryption that utilizes CTS is to be performed, and each of which operates in a same predetermined block cipher mode of operation and performs, when the CTS flag thereof is turned on, a complete encryption using a symmetric key cipher algorithm that utilizes CTS, while using a symmetric key;
an assigning unit configured to receive an input of a CTS signal indicating that second input data, that is input immediately after first input data having a block length, is shorter than the block length, to assign the first input data to one of the plurality of cryptographic processing circuits and to turn on the CTS flag of the one of the cryptographic processing circuits to which the first input data is assigned;
a concatenating unit that generates concatenated data by concatenating operation data generated during encrypting the first input data at the one of the cryptographic processing circuits and the second input data;
an output controlling unit that controls outputting the concatenated data to the one of the cryptographic processing circuits at which the first input data was encrypted, controls outputting first encrypted data obtained by encrypting the concatenated data at the one of the cryptographic processing circuits, and controls outputting second encrypted data obtained by encrypting the first input data at the one of the cryptographic processing circuits, and turns off the CTS flag of the one of the cryptographic processing circuits; and
a single register that stores the second input data while the one of the cryptographic processing circuits, operating in the predetermined block cipher mode, completely encrypts the first input data, wherein the single register stores the second encrypted data while the one of the cryptographic processing circuits, operating in the predetermined block cipher mode, completely encrypts the concatenated data.
2. The apparatus according to claim 1, wherein
the assigning unit stores the second input data into the single register,
the one of the cryptographic processing circuits encrypts using the symmetric key cipher algorithm that utilizes CTS on the first input data so as to generate the operation data and the second encrypted data,
the output controlling unit controls outputting the operation data and the second input data stored in the register to the concatenating unit, and
the one of the cryptographic processing circuits encrypts using the symmetric key cipher algorithm that utilizes CTS on the concatenated data so as to generate the first encrypted data.
3. The apparatus according to claim 2, wherein the output controlling unit stores the second encrypted data into the single register from which the second input data is output and, after controlling outputting the first encrypted data, the output controlling unit controls outputting the second encrypted data stored in the single register.
4. The apparatus according to claim 1, wherein
the assigning unit outputs a data length of the second input data to the concatenating unit, and
the concatenating unit concatenates the operation data with the second input data according to the data length.
5. A memory system, comprising:
a plurality of cryptographic processing circuits, each of which includes a flag storage unit that stores therein a CipherText Stealing (CTS) flag indicating whether an encryption that utilizes CTS is to be performed, and each of which operates in a same predetermined block cipher mode of operation and performs, when the CTS flag thereof is turned on, a complete encryption using a symmetric key cipher algorithm that utilizes CTS, while using a symmetric key;
an assigning unit configured to receive an input of a CTS signal indicating that second input data, that is input immediately after first input data having a block length, is shorter than the block length, to assign the first input data to one of the plurality of cryptographic processing circuits and to turn on the CTS flag of the one of the cryptographic processing circuits to which the first input data is assigned;
a concatenating unit that generates concatenated data by concatenating operation data generated during encrypting the first input data at the one of the cryptographic processing circuits and the second input data;
an output controlling unit that controls outputting the concatenated data to the one of the cryptographic processing circuits at which the first input data was encrypted, controls outputting first encrypted data obtained by encrypting the concatenated data at the one of the cryptographic processing circuits, and controls outputting second encrypted data obtained by encrypting the first input data at the one of the cryptographic processing circuits, and turns off the CTS flag of the one of the cryptographic processing circuits; and
a single register that stores the second input data while the one of the cryptographic processing circuits, operating in the predetermined block cipher mode, completely encrypts the first input data, wherein the single register stores the second encrypted data while the one of the cryptographic processing circuits, operating in the predetermined block cipher mode, completely encrypts the concatenated data; and
a memory that stores therein encrypted data that is output from the one of the cryptographic processing circuits.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An itaconic acid polymer or copolymer comprising monomer units derived from itaconic acid, wherein said polymer is substantially free of tri-substituted vinyl monomer impurities and wherein no more than 5 mole % of the total carboxylic acid groups from all monomers are neutralized.
2. The polymer of claim 1 further comprising co-monomer units derived from at least one of acrylic acid, methacrylic acid or salts, esters, and anhydrides thereof, 2-acrylamido-2-methylpropane sulfonic acid (AMPS) or salts thereof, and combinations thereof.
3. The polymer of claim 1 comprising greater than about 25 mole % monomers derived from itaconic acid and less than about 75 mole % monomer derived from at least one of acrylic acid, methacrylic acid or salts, esters, and anhydrides thereof, AMPS or salts thereof, and combinations thereof.
4. The polymer of claim 1 having a number average molecular weight (Mn) of from about 500 to 100,000.
5. The polymer of claim 1 having a number average molecular weight (Mn) of from about 100 to about 500.
6. The polymer of claim 1 comprising monomer units derived from itaconic acid at from about 35 to about 60 mole % and monomer units derived from acrylic acid at from about 40 to about 65 mole %.
7. The polymer of claim 1 comprising monomer units derived from itaconic acid at from about 60 to about 70 mole % and monomer units derived from acrylic acid at from about 30 to about 40 mole %.
8. The polymer of claim 1 comprising monomer units derived from itaconic acid at from about 35 to about 70 mole %, monomer units derived from acrylic acid at from about 15 to about 30 mole % and monomer units derived from AMPS at from about 0.1 to about 20 mole %.
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12. The polymer of claim 1, where the polymer is from about 0.1 to about 60% esterified.
13. A process for preparing a polymer solution of the itaconic acid polymer of claim 1 comprising: preparing in an aqueous medium a monomer solution of itaconic acid and polymerizing at a polymerization temperature of greater than about 60\xb0 C. in the presence of from about 0.01 to about 5 mole % polymerization initiator, based on the total amount of said monomers, wherein the reaction mixture is free of metal promoters, and further comprising a step of pre-neutralizing said monomer solution with less than 5 mole % of a neutralizer per total acid group present within said monomer solution.
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26. A polymer formulation comprising a polymer of claim 1.
27. The polymer formulation of claim 1, comprising less than 0.5% ww unreacted monomer based on the total weight of the polymer present in the solution.
28. The polymer formulation of claim 1, characterized by a pH of greater than 1.8.
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38. A method of chelating metal ions from a solution comprising adding to a solution containing metal ions, or subject to containing metal ions, an itaconic acid polymer or copolymer according to claim 1.
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