1. Apparatus for processing data, said apparatus comprising:
a memory addressable with a memory address having a value within a memory address space, said memory address space having a plurality of domains, a domain comprising a set of memory addresses as defined by programmable domain specifying data;
data processing circuitry, responsive to program instructions fetched from memory addresses within said memory address space, configured to perform data processing operations;
diagnostic circuitry responsive to one or more signals within said apparatus, configured to perform diagnostic operations generating diagnostic data;
diagnostic function control circuitry, responsive to a determination of in which of said plurality of domains a memory address of a program instruction currently being executed is located, configured to selectively disable at least some diagnostic functions of said diagnostic circuitry; and
memory management circuitry, responsive to memory page table data, configured to define properties of pages of memory addresses within said memory address space, said memory address space containing a plurality of contiguous pages of memory addresses, and wherein said programmable domain specifying data is part of said memory page table data.
2. Apparatus as claimed in claim 1, wherein said diagnostic function control circuitry is responsive to diagnostic-capability-defining data associated with at least one of said plurality of domains and specifying which diagnostic functions are disabled when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
3. Apparatus as claimed in claim 2, wherein said diagnostic-capability-defining data specifies whether invasive diagnostic functions are disabled when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
4. Apparatus as claimed in claim 2, wherein said diagnostic-capability-defining data specifies whether non-invasive diagnostic functions are permitted when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
5. Apparatus as claimed in claim 1, wherein said diagnostic circuitry includes tracing circuitry responsive to data processing operations being executed to generate a stream of trace data.
6. Apparatus as claimed in claim 1, wherein said diagnostic circuitry includes code profiling circuitry responsive to memory addresses of program instructions being executed to generate code profiling data.
7. Apparatus as claimed in claim 1, wherein said diagnostic circuitry includes instruction breakpoint circuitry responsive to a memory address of a program instruction being executed matching a predetermined characteristic to trigger a diagnostic event.
8. Apparatus as claimed in claim 7, wherein said diagnostic event is one of halting processing operations upon said apparatus to permit debug by an external device and triggering a debug exception to initiated execution of debug exception handling code upon said apparatus.
9. Apparatus as claimed in claim 1, wherein said diagnostic circuitry includes data watchpoint circuitry responsive to a memory address of a data value being accessed matching a predetermined characteristic to trigger a diagnostic event.
10. Apparatus for processing data, said apparatus comprising:
memory means for storing data, said memory means addressable with a memory address having a value within a memory address space, said memory address space having a plurality of domains, a domain comprising a set of memory addresses as defined by programmable domain specifying data;
data processing means for performing data processing operations in response to program instructions fetched from memory addresses within said memory address space;
diagnostic means for performing diagnostic operations generating diagnostic data in response to one or more signals within said apparatus;
diagnostic function control means for selectively disabling at least some diagnostic functions of said diagnostic circuitry in response to a determination of in which of said plurality of domains a memory address of a program instruction currently being executed is located; and
memory management means for managing memory access, said memory management means, in response to memory page table data, defining properties of pages of memory addresses within said memory address space, said memory address space containing a plurality of contiguous pages of memory addresses, and wherein said programmable domain specifying data is part of said memory page table data.
11. A method of processing data, said method comprising the steps of:
storing data within a memory addressable with a memory address having a value within a memory address space, said memory address space having a plurality of domains, a domain comprising a set of memory addresses as defined by programmable domain specifying data;
performing, in response to program instructions fetched from memory addresses within said memory address space, data processing operations with data processing circuitry;
performing, in response to one or more signals within said apparatus, diagnostic operations with diagnostic circuitry to generate diagnostic data;
selectively disabling, in response to a determination of in which of said plurality of domains a memory address of a program instruction currently being executed is located, at least some diagnostic functions of said diagnostic circuitry with diagnostic function control circuitry; and
managing memory accesses with memory page table data defining properties of pages of memory addresses within said memory address space, said memory address space containing a plurality of contiguous pages of memory addresses, said programmable domain specifying data being part of said memory page table data.
12. A method as claimed in claim 11, wherein said selective disabling is responsive to diagnostic-capability-defining data associated with at least one of said plurality of domains and specifying which diagnostic functions are disabled when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
13. A method as claimed in claim 12, wherein said diagnostic-capability-defining data specifies whether invasive diagnostic functions are disabled when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
14. A method as claimed in claim 12, wherein said diagnostic-capability-defining data specifies whether non-invasive diagnostic functions are permitted when said memory address of said program instruction currently being executed is located in said at least one of said plurality of domains.
15. A method as claimed in claim 11, wherein said diagnostic circuitry includes tracing circuitry responsive to data processing operations being executed to generate a stream of trace data.
16. A method as claimed in claim 11, wherein said diagnostic circuitry includes code profiling circuitry responsive to memory addresses of program instructions being executed to generate code profiling data.
17. A method as claimed in claim 11, wherein said diagnostic circuitry includes instruction breakpoint circuitry responsive to a memory address of a program instruction being executed matching a predetermined characteristic to trigger a diagnostic event.
18. A method as claimed in claim 17, wherein said diagnostic event is one of halting processing operations upon said apparatus to permit debug by an external device and triggering a debug exception to initiated execution of debug exception handling code upon said apparatus.
19. A method as claimed in claim 11, wherein said diagnostic circuitry includes data watchpoint circuitry responsive to a memory address of a data value being accessed matching a predetermined characteristic to trigger a diagnostic event.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A switching unit for an electrical switching device, comprising:
a switching lock including a switching lock board, a switching mechanism and a rotor housing, the rotor housing including a contact arm disposed therein for opening and closing contacts during a rotation of the rotor housing about a rotation axis, the switching lock board being stationary during the rotation of the rotor housing; and
at least one lever apparatus, functionally connected at an upper end to the switching mechanism and functionally connected at a lower end by way of a connecting pin to a face of the rotor housing such that the at least one lever apparatus extends from the lower end to the upper end in a space that is between the switching lock board and the rotor housing, wherein at least one of the lower end of the at least one lever apparatus and the connecting pin includes at least one stop surface, configured to limit rotation of the rotor housing about the rotation axis at least in one direction by coming up against a stop of the switching lock board.
2. The switching unit of claim 1, wherein the connecting pin is configured as a separate component from the at least one lever apparatus and the rotor housing.
3. The switching unit of claim 2, wherein a pin holder is disposed on at least one face of the rotor housing, the pin holder being configured to accommodate the connecting pin.
4. The switching unit of claim 3, wherein the at least one lever apparatus includes a passage at the lower end, configured to accommodate the connecting pin.
5. The switching unit of claim 2, wherein the at least one lever apparatus includes a passage at the lower end, configured to accommodate the connecting pin.
6. The switching unit of claim 1, wherein the connecting pin extends at least in segments along a pin axis, disposed parallel or essentially parallel to the rotation axis of the rotor housing.
7. The switching unit of claim 1, wherein the connecting pin extends along a pin axis, disposed at a distance from the rotation axis of the rotor housing.
8. The switching unit of claim 1, wherein the at least one lever apparatus includes two lever apparatuses, and wherein on each face of the rotor housing, one of the two lever apparatuses is respectively functionally connected, at an upper end by way of the switching mechanism and at a lower end by way of a connecting pin, to a face of the rotor housing.
9. The switching unit of claim 1, wherein the connecting pin is configured in an integral manner with the rotor housing or with the at least one lever apparatus.
10. An electrical switching device, comprising at least one switching unit of claim 1.
11. The electrical switching device of claim 10, wherein the electrical switching device is a circuit breaker.
12. The switching unit of claim 1, wherein the switching unit is for a circuit breaker.
13. The switching unit of claim 1, wherein the switching lock board includes two parallel plates, between which the switching mechanism is arranged, and the stop includes two stop portions at same positions on each of the two parallel plates.
14. The switching unit of claim 1, wherein the stop is a recessed portion of the switching lock board.
15. A switching unit for an electrical switching device, comprising:
a switching lock including a switching lock board, a switching mechanism and a rotor housing, the rotor housing including a contact arm disposed therein for opening and closing contacts during a rotation of the rotor housing about a rotation axis, the switching lock board being stationary during rotation of the rotor housing; and
at least one lever apparatus, functionally connected at an upper end to the switching mechanism and functionally connected at a lower end by way of a connecting pin to a face of the rotor housing such that the at least one lever apparatus extends from the lower end to the upper end in a space that is between the switching lock board and the rotor housing, wherein a pin holder is disposed on the face of the rotor housing, the pin holder being configured to accommodate the connecting pin such that the connecting pin does not penetrate an inner wall of the rotor housing.
16. The switching unit of claim 15, wherein at least one of the lower end of the at least one lever apparatus and the connecting pin includes at least one stop surface, configured to limit rotation of the rotor housing about the rotation axis at least in one direction by coming up against a stop of the switching lock board.