1. An integrated circuit interconnect structure formed on a substrate, the interconnect structure comprising:
a conformal cobalt nitride layer located on a substrate surface defining an interconnect structure; and
a conductive layer comprising copper located over the cobalt nitride layer.
2. The structure of claim 1 further comprising a diffusion barrier between the cobalt nitride layer and the substrate.
3. The structure of claim 1 wherein the cobalt nitride has the composition COxN, with x lying between about 1 and 10.
4. The structure of claim 1 wherein the cobalt nitride has the composition COxN, with x lying between about 2 and 6.
5. The structure of claim 1 wherein the cobalt nitride has the composition COxN, with x lying between about 3 and 5.
6. The structure of claim 2 in which the diffusion barrier is selected from the group consisting of tantalum nitride, tantalum carbide, tungsten nitride, tungsten carbide and mixtures thereof.
7. The interconnect structure according to claim 1 wherein the cobalt nitride layer is a chemical vapor deposited layer.
8. The interconnect structure according to claim 2 wherein the diffusion barrier layer is a chemical vapor deposited layer.
9. The interconnect structure according to claim 1 wherein at least part of the copper-comprising conductive layer is a chemical vapor deposited layer.
10. The interconnect structure according to claim 1 wherein at least part of the copper-comprising conductive layer is an electrochemically deposited layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-20. (canceled)
21. A real-time operating system (RTOS) for use with a minimal-memory controller, comprising:
a kernel managing task execution, including context switching, executing from a machine readable medium on the controller;
a plurality of defined tasks as code sets, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks; and
a single, general-purpose call-return stack common to all of the defined tasks;
wherein a task-resume address is obtained in a context switch directly from the single, general-purpose call-return stack.
22. The RTOS of claim 21 wherein the single call-return stack is implemented as a hardware call-return stack.
23. The RTOS of claim 21 comprising a specific task-control block assigned to each task, wherein a single task-resume address is saved.
24. The RTOS of claim 23 wherein processor state information is also saved.
25. The RTOS of claim 21 wherein a label is placed at the point where a task is to resume, and the address of the label is saved as the task-resume address.
26. The RTOS of claim 25 wherein multiple labels are used within a single task to accomplish multiple context switches.
27. The RTOS of claim 21 further comprising a wait-on-event function characterized in that the function is called only at task-level, returns a value based on whether an event is available or not, and initiates a context switch or not based on the returned value.
28. The RTOS of claim 21 further comprising a wait-on-event function enclosed within a (while) loop at task level, and characterized in that the task calls the wait-on-event function in the loop and examines its return code, exiting the loop if the event is available and initiates a context switch if not, and in the event of a context switch, the task recalls the wait-on-event function after resumption, being still in the loop, and repeats this procedure until exiting the loop.
29. A method for context-switching in a minimal-memory controller, comprising the steps of:
(a) managing task execution, including context switching, by a kernel executing from a machine readable medium on the controller;
(b) implementing a plurality of defined tasks as code sets, individual ones of the tasks having subroutines callable in nested levels for accomplishing the tasks; and
(c) providing a single, general-purpose call-return stack common to all of the defined tasks; and
(d) obtaining a task-resume address in a context switch directly from the single call-return stack.
30. The method of claim 29 wherein the single call-return stack is implemented as a hardware call-return stack.
31. The method of claim 29 comprising a specific task-control block assigned to each task, wherein a single task-resume address is saved.
33. The method of claim 31 wherein processor state information is also saved.
34. The method of claim 29 wherein a label is placed at the point where a task is to resume, and the address of the label is saved as the task-resume address.
35. The method of claim 34 wherein multiple labels are used within a single task to accomplish multiple context switches.
36. The method of claim 29 further comprising a wait-on-event function characterized in that the function is called only at task-level, returns a value based on whether an event is available or not, and initiates a context switch or not based on the returned value.
37. The method of claim 29 further comprising a wait-on-event function enclosed within a (while) loop at task level, and characterized in that the task calls the wait-on-event function in the loop and examines its return code, exiting the loop if the event is available and initiates a context switch if not, and in the event of a context switch, the task recalls the wait-on-event function after resumption, being still in the loop, and repeats this procedure until exiting the loop.