1. A connector, comprising:
a housing with an opening defining an interior of the housing;
at least one terminal fitting accommodated in the housing;
a wire connected with the terminal fitting;
at least one seal mounted on the wire and fit into the opening in the housing for sealing the interior of the housing; and
a holder having a cap shape with a back wall and a surrounding wall projecting forward from the back wall, the holder being mountable on a mounting portion of the housing from a mounting side, the back wall being formed with at least one wire insertion hole for receiving the wire drawn out from the housing, the back wall of the holder further having an inner fitting to be fit into the mounting portion while holding the mounting portion in a thickness direction together with the surrounding wall;
at least one leading-end widened rib extending in substantially forward and backward directions on one of an inner circumferential surface of the surrounding wall and an outer circumferential surface of the mounting portion, the leading-end widened rib having a leading end wider than a base end; and
at least one recess on the other of the inner circumferential surface of the surrounding wall and the outer circumferential surface of the mounting portion at a position substantially corresponding to the leading-end widened rib, the recess having a shape corresponding to the leading-end widened rib for dovetail engagement therewith, one of the leading-end widened rib and the recess extending substantially up to the back wall of the holder.
2. The connector of claim 1, wherein: the surrounding wall of the holder is substantially cylindrical, the leading-end widened rib is provided on the inner circumferential surface of the surrounding wall, and
at least one recessed groove is formed in the outer circumferential surface of the surrounding wall at a position substantially having a back-to-back relationship with the leading-end widened rib.
3. The connector of claim 1, wherein the mounting portion is substantially tubular and has an open rear surface.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a transistor surrounded by an isolation structure, the method comprising:
prior to forming said isolation structure, selectively forming a semiconductor material on an exposed region of a semiconducting substrate;
after selectively forming said semiconductor material, forming at least one pad layer above said substrate and said semiconductor material, wherein said at least one pad layer is comprised of an insulating material;
forming a trench that extends through said at least one pad layer and into said substrate, wherein said trench extends around said semiconductor material;
forming said isolation structure in said trench around said semiconductor material; and
forming a gate structure above said semiconductor material.
2. The method of claim 1, wherein selectively forming said semiconductor material comprises performing an epitaxial deposition process to form a semiconductor material comprised of silicongermanium or germanium on said exposed region of said semiconducting substrate.
3. The method of claim 1, wherein said semiconducting substrate is a bulk semiconducting substrate or an active layer of a silicon-on-insulator (SOI) substrate.
4. The method of claim 1, wherein said transistor is a PFET transistor and wherein said semiconductor material is comprised of silicongermanium.
5. The method of claim 1, wherein, prior to selectively forming said semiconductor material on said exposed region of said substrate, the method further comprises forming at least one alignment mark in said semiconducting substrate.
6. The method of claim 1, wherein, prior to selectively forming said semiconductor material on said exposed region of said substrate, the method further comprises forming a recess in said substrate and wherein selectively forming said semiconductor material comprises selectively forming said semiconductor material in said recess.
7. The method of claim 1, wherein said isolation structure is a shallow trench isolation structure.
8. The method of claim 1, wherein said gate structure is either a sacrificial gate structure or a final gate structure for said transistor.
9. The method of claim 1, wherein said gate structure is comprised of at least a gate insulation layer and a conductive gate electrode.
10. A method of forming a PFET transistor surrounded by an isolation structure, the method comprising:
prior to forming said isolation structure, performing an epitaxial deposition process to selectively form a semiconductor material comprised of silicongermanium or germanium on an exposed region of a semiconducting substrate;
after selectively forming said semiconductor material, forming at least one pad layer above said substrate and said semiconductor material, wherein said at least one pad layer is comprised of an insulating material;
forming a trench that extends through said at least one pad layer and into said substrate, wherein said trench extends around said semiconductor material;
forming said isolation structure in said trench around said semiconductor material; and
forming a gate structure above said semiconductor material.
11. The method of claim 10, wherein, prior to performing said epitaxial deposition process to selectively form said semiconductor material on said exposed region of said substrate, the method further comprises forming at least one alignment mark in said semiconducting substrate.
12. The method of claim 10, wherein, prior to performing said epitaxial deposition process to selectively form said semiconductor material on said exposed region of said substrate, the method further comprises forming a recess in said substrate and wherein performing said epitaxial deposition process to selectively form said semiconductor material comprises performing said epitaxial deposition process to selectively form said semiconductor material in said recess.
13. A method of forming a first transistor surrounded by a first isolation structure and a second transistor surrounded by a second isolation structure, the method comprising:
prior to forming either of said first or second isolation structures, selectively forming a semiconductor material on an exposed first region of a semiconducting substrate where said first transistor will be formed;
after selectively forming said semiconductor material, forming at least one pad layer above said substrate and said semiconductor material, wherein said at least one pad layer is comprised of an insulating material;
forming first and second trenches that extend through said at least one pad layer and into said substrate, wherein said first trench is formed around said semiconductor material and said second trench is formed around a second region of said substrate where said second transistor will be formed;
forming said first and second isolation structures in said first and second trenches, respectively;
forming a first gate structure for said first transistor above said semiconductor material positioned on said first region of said substrate; and
forming a second gate structure for said second transistor above said second region of said substrate.
14. The method of claim 13, wherein selectively forming said semiconductor material comprises performing an epitaxial deposition process to selectively form a semiconductor material comprised of silicongermanium or germanium on said first region of said semiconducting substrate.
15. The method of claim 13, wherein said first transistor is a PFET transistor, said second transistor is an NFET transistor and wherein said semiconductor material is comprised of silicongermanium.
16. The method of claim 13, wherein, prior to selectively forming said semiconductor material on said exposed first region of said substrate, the method further comprises forming at least one alignment mark in said semiconducting substrate.
17. The method of claim 13, wherein, prior to selectively forming said semiconductor material on said exposed first region of said substrate, the method further comprises forming a recess in said substrate and wherein selectively forming said semiconductor material comprises selectively forming said semiconductor material in said recess.
18. The method of claim 13, wherein forming said first and second trenches comprises performing a common etching process to define said first trench and said second trench.
19. A method of forming a PFET transistor surrounded by a first isolation structure and an NFET transistor surrounded by a second isolation structure, the method comprising:
prior to forming either of said first or second isolation structures, performing an epitaxial deposition process to selectively form a semiconductor material comprised of silicongermanium or germanium on an exposed first region of a semiconducting substrate where said PFET transistor will be formed;
after selectively forming said semiconductor material, forming at least one pad layer above said substrate and said semiconductor material, wherein said at least one pad layer is comprised of an insulating material;
forming first and second trenches that extend through said at least one pad layer and into said substrate, wherein said first trench is formed around said semiconductor material and said second trench is formed around a second region of said substrate where said NFET transistor will be formed;
forming said first and second isolation structures in said first and second trenches, respectively;
forming a first gate structure for said PFET transistor above said semiconductor material positioned on said first region of said substrate; and
forming a second gate structure for said NFET transistor above said second region of said substrate.
20. The method of claim 19, wherein, prior to performing said epitaxial deposition process to selectively form said semiconductor material on said exposed first region of said substrate, the method further comprises forming at least one alignment mark in said semiconducting substrate.
21. The method of claim 19, wherein, prior to performing said epitaxial deposition process to selectively form said semiconductor material on said exposed first region of said substrate, the method further comprises forming a recess in said substrate and wherein selectively forming said semiconductor material comprises selectively forming said semiconductor material in said recess.
22. The method of claim 19, wherein forming said first and second trenches in said substrate comprises performing a common etching process to define said first trench and said second trench.
23. A method of forming a first transistor surrounded by a first isolation structure and a second transistor surrounded by a second isolation structure, the method comprising:
prior to forming either of said first or second isolation structures, forming at least one alignment mark in a semiconducting substrate;
after forming said at least one alignment mark, forming a patterned layer of insulating material above said substrate wherein said patterned layer of insulating material exposes a first region of said semiconducting substrate where said first transistor will be formed;
selectively forming a semiconductor material on said exposed first region of said substrate;
after selectively forming said semiconductor material, removing said patterned layer of insulating material and forming at least one pad layer above said substrate and said semiconductor material, wherein said at least one pad layer is comprised of an insulating material;
forming first and second trenches that extend through said at least one pad layer and into said substrate, wherein said first trench is formed around said semiconductor material and said second trench is formed around a second region of said substrate where said second transistor will be formed;
forming said first and second isolation structures in said first and second trenches, respectively;
forming a first gate structure for said first transistor above said semiconductor material positioned on said first region of said substrate; and
forming a second gate structure for said second transistor above said second region of said substrate.
24. The method of claim 23, wherein selectively forming said semiconductor material comprises performing an epitaxial deposition process to selectively form a semiconductor material comprised of silicongermanium or germanium on said first region of said semiconducting substrate.
25. The method of claim 23, wherein said first transistor is a PFET transistor, said second transistor is an NFET transistor and wherein said semiconductor material is comprised of silicongermanium.
26. The method of claim 23, wherein, prior to selectively forming said semiconductor material on said first region of said substrate, the method further comprises forming a recess in said substrate and wherein selectively forming said semiconductor material comprises selectively forming said semiconductor material in said recess.
27. The method of claim 23, wherein forming said first and second trenches comprises performing a common etching process to define said first trench and said second trench.