1. A method for designing an interposer, the method comprising:
determining a ball grid array (BGA) region in the interposer;
determining first stress concentration regions in the interposer, the first stress concentration regions extending from a first side of the interposer to a second side of the interposer, wherein the first stress concentration regions extend above regions each configured to receive at least one ball, wherein a diameter of the first stress concentration regions is 20% to 30% larger than a diameter of the at least one ball;
designing a layout for active through vias in the interposer, wherein at least one active through via is placed outside the first stress concentration regions, and wherein no active through vias are placed within the first stress concentration regions; and
designing a layout for dummy through vias in the interposer, wherein at least one dummy through via is placed within the first stress concentration regions.
2. The method of claim 1, further comprising:
determining a controlled collapse chip connection (C4) bumps region; and
determining at least one second stress concentration region in the interposer, the at least one second stress concentration region extending from the second side of the interposer to the first side of the interposer,
wherein designing the layout for the active through vias further comprises placing the at least one active through via outside the at least one second stress concentration region, and
wherein designing the layout for the dummy through vias further comprises placing at least one second dummy through via within the at least one second stress concentration region.
3. The method of claim 2, wherein the C4 bumps region is designed to receive at least one C4 bump, wherein a diameter of the at least one second stress concentration region is 10% to 20% larger than a diameter of the at least one C4 bump.
4. The method of claim 1, wherein designing the layout for the active through vias and designing the layout for the dummy through vias further comprises determining a ratio of active through vias and dummy through vias for the at least one ball to redistribute localized stress in a package-on-package structure.
5. A method for forming a package-on-package structure, the method comprising:
providing a substrate having a plurality of balls, the plurality of balls including at least one ball electrically connected to the substrate;
providing a semiconductor chip;
forming an interposer having a first side and a second side opposite the first side, the interposer electrically connecting the substrate and the semiconductor chip;
forming at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside at least one exclusion zone, the at least one exclusion zone extending through the interposer above each of the plurality of balls, and wherein no active through vias are formed within the at least one exclusion zone; and
forming at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one exclusion zone.
6. The method of claim 5, wherein forming at least one active through via and forming at least one dummy through via further comprises forming the at least one active through via and the at least one dummy through via for at least one ball of the plurality of balls, wherein a ratio of active through vias and dummy through vias to the at least one ball of the plurality of balls redistributes localized stress in the package-on-package structure.
7. The method of claim 6, wherein the ratio comprises one active through via and eight dummy through vias for the at least one ball of the plurality of balls.
8. The method of claim 6, wherein the ratio comprises one active through via and four dummy through vias for the at least one ball of the plurality of balls.
9. The method of claim 5, wherein forming the interposer comprises forming a multi-layer interposer, wherein the first side of the interposer comprises a first ILD layer, a second ILD layer, and a metallization layer.
10. The method of claim 9, wherein the first ILD layer comprises an oxide, a nitride, a polymer, or a combination thereof, the second ILD layer comprises low temperature polybenzoxazole (LTPBO), an oxide, a nitride, a polymer, or a combination thereof, and the metallization layer comprises copper, aluminum, nickel, or combinations thereof, the method further comprising forming an under bump metallization (UBM) layer electrically connecting the metallization layer with at least one of the plurality of balls.
11. The method of claim 5, further comprising forming at least one second dummy through via within at least one second exclusion zone, the at least one second exclusion zone extending from the second side of the interposer to the first side of the interposer below at least one controlled collapse chip connection (C4) bump connected to the semiconductor chip, wherein the at least one active through via is formed outside the at least one second exclusion zone and wherein no active through vias are formed within the at least one second exclusion zone.
12. The method of claim 11, wherein forming the interposer comprises forming a multi-layer interposer, wherein the second side of the interposer comprises a first ILD layer, a second ILD layer, and a metallization layer.
13. The method of claim 12, wherein the first ILD layer comprises an oxide, a nitride, a polymer, or combinations thereof, the second ILD layer comprises a passivation layer, low temperature polybenzoxazole (LTPBO), an oxide, a nitride, a polymer, or combinations thereof, and the metallization layer comprises copper, aluminum, gold, silver, nickel, or combinations thereof, the method further comprising forming an under bump metallization (UBM) layer electrically connecting the metallization layer with the at least one C4 bump.
14. A method for forming a packaging structure, the packaging structure comprising a substrate, an interposer, and a semiconductor chip, the method comprising:
electrically connecting the substrate and the interposer using a plurality of balls including at least one ball electrically connected to the substrate;
electrically connecting the interposer and the semiconductor chip using a plurality of connectors;
forming active through vias extending from a first side of the interposer to a second side of the interposer opposite the first side, wherein the active through vias are formed outside first pre-determined stress concentration regions in the interposer, wherein the first pre-determined stress concentration regions are centered above respective balls of the plurality of balls; and
forming dummy through vias extending from the first side of the interposer to the second side of the interposer, wherein at least one dummy through via is formed within at least one of the first pre-determined stress concentration regions.
15. The method of claim 14, wherein the plurality of connectors comprises at least one of C4 bumps, \u03bcbumps, and copper pillars.
16. The method of claim 14, wherein a diameter of the first pre-determined stress concentration regions is 20% to 30% larger than a diameter of at least one of the plurality of balls.
17. The method of claim 14, further comprising forming at least one second dummy through via within at least one second pre-determined stress concentration region in the interposer, wherein the second pre-determined stress concentration region is centered below a respective connector of the plurality of connectors.
18. The method of claim 17, wherein the active through vias are formed outside the at least one second pre-determined stress concentration region.
19. The method of claim 17, wherein a diameter of the at least one second pre-determined stress concentration region is 10% to 20% larger than a diameter of the respective connector of the plurality of connectors.
20. The method of claim 14, wherein forming the active through vias and forming the dummy through vias further comprises forming a pre-determined number of active through vias and a pre-determined number of dummy through vias for at least one ball of the plurality of balls.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A reactor with mitigation of fouling-related pressure buildup, said reactor comprising:
(1) a reactor vessel having an inlet and an outlet;
(2) at least one bed of catalyst particles located within said reactor vessel;
(3) at least one top layer of inert particulate material or catalytically active particulate material adjacent to and on top of said at least one bed of catalyst particles provided that any catalytically active particulate material in the top layer can withstand jetting fluids;
(4) at least one blowback ring embedded within said top layer, said at least one blowback ring containing a plurality of jets for upwardly directing fluid passing through said at least one blowback ring.
2. The reactor of claim 1 wherein the fluid in the blowback ring is at least one of gas or liquid.
3. The reactor of claim 2 wherein the fluid is a mixture of gas and liquid.
4. The reactor of claim 1 wherein the layer of inert particulate material is comprised of spheres.
5. The reactor of claim 4 wherein the spheres are graded according to at least one of size or shape.
6. The reactor of claim 1 wherein the layer of inert particulate material is non-spherical in shape.
7. The reactor of claims 4 or 6 wherein the inert particulate material is porous.
8. The reactor of claims 4 or 6 wherein the inert particulate material is non-porous.
9. The reactor of claim 6 wherein the inert particulate material is graded according to at least one of size or shape.
10. The reactor of claim 1 wherein the top layer is an inert particulate material.
11. A process for mitigating fouling in a reactor, said process comprising:
(a) providing a reactor vessel having an inlet and an outlet;
(b) providing at least one bed of hydroprocessing catalyst particles located within said reactor vessel;
(c) providing at least one top layer of inert particulate material or catalytically active particulate material adjacent to and on top of said at least one bed of hydroprocessing catalyst particles provided that any catalytically active particulate material in the top layer can withstand jetting fluids;
(d) embedding at least one blowback ring within said top layer, said at least one blowback ring containing a plurality of jets for upwardly directing fluid passing through said at least one blowback ring;
(e) passing a feedstock through the reactor under hydroprocessing conditions; and
(f) passing fluids through the blowback ring jets at a velocity sufficient to dislodge any foulants that accumulate on or within the top layer.
12. The process of claim 11 wherein the fluid in the blowback ring is at least one of gas or liquid.
13. The process of claim 11 wherein the fluid is a mixture of gas and liquid.
14. The process of claim 11 wherein the layer of inert particulate material is comprised of spheres.
15. The process of claim 14 wherein the spheres are graded according to at least one of size or shape.
16. The process of claim 11 wherein the layer of inert particulate material is non-spherical in shape.
17. The process of claim 16 wherein the inert particulate material is graded according to at least one of size or shape.
18. The process of claims 14 or 16 wherein the inert particulate material is porous.
19. The process of claims 14 or 16 wherein the inert particulate material is non-porous.
20. The process of claim 11 wherein hydroprocessing conditions include temperatures of from 150 to 400\xb0 C., pressures of from 790 to 20,786 kPa (100 to 3000 psig), liquid hourly space velocities from 0.1 to 20 hr\u22121 and hydrogen treat gas rates from 17.8 to 1780 m3m3 (100 to 10,000 scfB).
21. The process of claim 11 wherein the fluids comprise hydrogen, treat gas, nitrogen and light petroleum gases, liquids or mixtures thereof.