1. A method of operating a packet-processing device comprising:
receiving a point-to-point protocol packet stream from a point-to-point protocol peer over a point-to-point full-duplex data link;
analyzing whether conditions at the device support an adjustment in the flow rate of the received packet stream; and
when an adjustment in the flow rate is supported, generating a point-to-point protocol flow control frame requesting that the peer adjust the flow rate of the packet stream, and sending the point-to-point protocol flow control frame to the peer over the data link while the packet-processing device is receiving the point-to-point protocol packet stream.
2. The method of claim 1, wherein analyzing whether conditions at the device support an adjustment in the flow rate of the packet stream comprises:
estimating the average flow rate of the packet stream over a selected period of time;
comparing the average flow rate to an allocated flow rate for that packet stream; and
when the average flow rate exceeds the allocated flow rate, indicating support for a decrease in the flow rate of that packet stream.
3. The method of claim 1, wherein analyzing whether conditions at the device support an adjustment in the flow rate of the packet stream comprises:
examining the condition of a receive buffer in the device;
comparing the receive buffer condition to target receive buffer conditions; and
indicating support for an adjustment in the flow rate of the packet stream when the receive buffer condition falls outside the target receive buffer conditions.
4. The method of claim 3, wherein comparing the receive buffer condition to target receive buffer conditions comprises comparing receive buffer fullness to a target receive buffer fullness.
5. The method of claim 3, wherein examining receive buffer condition comprises predicting a future value of receive buffer fullness using a current value of receive buffer fullness and a calculated rate of change in buffer fullness.
6. The method of claim 1, wherein when a downward adjustment in the flow rate is supported, the generated flow control frame requests that the peer pause all data packet flow for a pause time.
7. The method of claim 6, wherein the generated flow control frame contains a payload conforming to an accepted format for an IEEE802.3x MAC control frame payload.
8. The method of claim 1, wherein when a downward adjustment in the flow rate is supported, the generated flow control frame indicates a decrease for at least one priority from a set of flow priorities.
9. The method of claim 8, wherein a given priority corresponds to a service class, and is accompanied by a request that the peer pause data packet flow for a pause time, for that service class.
10. The method of claim 9, wherein the generated flow control frame contains requests corresponding to multiple service classes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit comprising:
a command buffer configured to (i) buffer a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and
a read buffer configured to transmit a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.
2. The circuit according to claim 1, further comprising a controller circuit configured to control at least one of a memory circuit, a semaphore block and a mailbox block for reading said read signal.
3. The circuit according to claim 2, wherein said controller circuit is couplable to a communication channel configured to generate said read signal.
4. The circuit according to claim 1, further comprising a write queue configured to receive a write signal within a plurality of second transfers.
5. The circuit according to claim 4, further comprising a controller circuit configured to control at least one block of a memory block, a semaphore block and a mailbox block for writing said write signal.
6. The circuit according to claim 4, wherein said controller circuit is further configured to transmit said write signal from said circuit within a plurality of third transfers.
7. The circuit according to claim 1, further comprising a state machine configured to control reads and writes to a memory circuit storing said read signal.
8. The circuit according to claim 7, further comprising a timing circuit configured to control timing of a plurality of control signals to said memory circuit.
9. The circuit according to claim 8, further comprising an address decoder configured to transfer an address signal to said state machine in response to said each said read command.
10. The circuit according to claim 9, further comprising a plurality of registers configured to store protocol information for communicating with said memory circuit.
11. A method of operating a circuit, comprising the steps of:
(A) buffering a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values;
(B) transmitting a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and
(C) transmitting a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.
12. The method according to claim 11, further comprising the step of buffering said read signal received by said circuit within a plurality of second transfers prior to transmitting said read signal within said first transfers.
13. The method according to claim 11, further comprising the step of storing said read signal in said circuit prior to transmitting said read signal within said first transfers.
14. The method according to claim 11, further comprising the step of transmitting a valid signal from said circuit in response to servicing said particular read command, said valid signal locating said read signal within said plurality of transfers.
15. The method according to claim 11, further comprising the step of transmitting an acknowledge signal from said circuit when ready to buffer a new read command to said read commands in response to receiving a request signal.
16. The method according to claim 11, further comprising the step of queuing a write signal received by said circuit within a plurality of second transfers.
17. The method according to claim 16, further comprising the step of extracting said write signal from said second transfers in response to a valid signal locating said write signal within said second transfers.
18. The method according to claim 16, further comprising the step of storing said write signal in said circuit after queuing said write signal.
19. The method-according to claim 16, further comprising the step of transmitting said write signal from said circuit within a plurality of third transfers.
20. A circuit comprising,
means for buffering a plurality of read commands received by said circuit, wherein each said read command has one of a plurality of port values and one of a plurality of identification values;
means for transmitting a tag signal from said circuit in response to servicing a particular read command of said read commands, said tag signal having a particular port value of said port values and a particular identification value of said identification values as determined by said particular read command; and
means for transmitting a read signal within a plurality of first transfers from said circuit in response to servicing said particular read command.
21. A system comprising:
a plurality of controller circuits each configured to store data;
a plurality of line buffer circuits each configured to transfer said data between an accessed one of said controller circuits and one of a plurality of first busses; and
a first arbiter circuit configured to control access to said controller circuits by said line buffer circuits.
22. The system according to claim 21, further comprising a second arbiter circuit configured to control access at least one of said controller circuits by said line buffer circuits.
23. The system according to claim 22, wherein at least two of said line buffer circuits access at least two of said controller circuits substantially simultaneously.
24. The system according to claim 21, further comprising a circuit configured to transfer configuration data between a second bus and (i) said line buffer circuits, (ii) said first arbiter circuit and (iii) said controller circuits.
25. A system comprising:
a plurality of controller circuits each configured to store data;
a plurality of line buffer circuits each configured to transfer said data between an accessed one of said controller circuits and one of a plurality of first busses; and
a plurality of arbiter circuits each configured to control access to at least one of said controller circuits by said line buffer circuits.
26. The system according to claim 25, wherein at least two of said line buffer circuits access at least two of said controller circuits substantially simultaneously.
27. The system according to claim 25, wherein access to at least two of said controller circuits is arbitrated by one of said arbiter circuits.
28. The system according to claim 25, further comprising a circuit configured to transfer configuration data between a second bus and (i) said line buffer circuits, (ii) arbiter circuits and (iii) said controller circuits.