1. A three-phase voltage tripler, comprising:
first, second, and third capacitive elements; and
a switching module that selectively switches connections among said capacitive elements and between said capacitive elements and a reference voltage during first, second, and third periods,
wherein said switching module charges said first capacitive element to a first voltage level during said first period, said second capacitive element to a second voltage level during said second period, and said third capacitive element to a third voltage level during said third period, and wherein said third voltage level is greater than said second voltage level and said second voltage level is greater than said first voltage level.
2. The three-phase voltage tripler of claim 1 wherein said first voltage level is approximately equal to said reference voltage, said second voltage level is approximately equal to two times said first voltage level, and said third voltage is approximately equal to three times said first voltage level.
3. The three-phase voltage tripler of claim 1 wherein said switching module comprises:
a plurality of switches; and
a clock module that generates clock signals that selectively control said plurality of switches.
4. The three-phase voltage tripler of claim 3 wherein said plurality of switches comprise:
a first transistor having a first terminal that communicates with said reference voltage, a control terminal, and a second terminal that communicates with a first end of said first capacitive element;
a second transistor having a first terminal that communicates with said second terminal of said first transistor, a control terminal, and a second terminal that communicates with a first end of said second capacitive element;
a third transistor having a first terminal that communicates with said second terminal of said second transistor, a control terminal, and a second terminal that communicates with a first end of said third capacitive element,
wherein said clock module selectively biases said first, second, and third transistors during said first, second, and third periods.
5. The three-phase voltage tripler of claim 1 wherein substantially the same peak current is drawn during said first, second, and third periods from a source of said reference voltage when said three-phase voltage tripler supplies a predetermined load current.
6. The three-phase voltage tripler of claim 1 wherein during said first period, a first end of said first capacitive element communicates with said reference voltage and a second end of said first capacitive element communicates with a common voltage.
7. The three-phase voltage tripler of claim 6 wherein during said second period, said first end of said first capacitive element communicates with a first end of said second capacitive element, said second end of said first capacitive element communicates with said reference voltage, and a second end of said second capacitive element communicates with said common voltage.
8. The three-phase voltage tripler of claim 7 wherein during said third period, said first end of said second capacitive element communicates with a first end of said third capacitive element, said second end of said second capacitive element communicates with said reference voltage, and a second end of said third capacitive element communicates with said common voltage.
9. A method, comprising:
arranging first, second, and third capacitive elements;
selectively switching connections among said capacitive elements and between said capacitive elements and a reference voltage during first, second, and third periods; and
charging said first capacitive element to a first voltage level during said first period, said second capacitive element to a second voltage level during said second period, and said third capacitive element to a third voltage level during said third period, wherein said third voltage level is greater than said second voltage level and said second voltage level is greater than said first voltage level.
10. The method of claim 9 wherein said first voltage level is approximately equal to said reference voltage, said second voltage level is approximately equal to two times said first voltage level, and said third voltage is approximately equal to three times said first voltage level.
11. The method of claim 9 further comprising:
arranging a plurality of switches;
generating clock signals that selectively control said plurality of switches; and
communicating among said capacitive elements, said switches, and said reference voltage based on said clock signals.
12. The method of claim 11 further comprising including first, second, and third transistors in said switches, wherein each of said transistors has first, second, and control terminals, and further comprising:
communicating between said first terminal of said first transistor and said reference voltage;
communicating between said second terminal of said first transistor and a first end of said first capacitive element;
communicating between said first terminal of said second transistor and said second terminal of said first transistor;
communicating between said second terminal of said second transistor and a first end of said second capacitive element;
communicating between said first terminal of said third transistor and said second terminal of said second transistor;
communicating between said second terminal of said third transistor and a first end of said third capacitive element;
communicating said clock signals to said control terminals of said transistors; and
selectively biasing said transistors during said first, second, and third periods.
13. The method of claim 9 further comprising drawing substantially the same peak current during said first, second, and third periods from a source of said reference voltage when supplying a predetermined load current.
14. The method of claim 9 further comprising communicating during said first period between a first end of said first capacitive element and said reference voltage, and between a second end of said first capacitive element and a common voltage.
15. The method of claim 14 further comprising communicating during said second period between said first end of said first capacitive element and a first end of said second capacitive element, between said second end of said first capacitive element and said reference voltage, and between a second end of said second capacitive element and said common voltage.
16. The method of claim 15 further comprising communicating during said third period between said first end of said second capacitive element and a first end of said third capacitive element, between said second end of said second capacitive element and said reference voltage, and between a second end of said third capacitive element and said common voltage.
17. A three-phase voltage tripler, comprising:
first, second, and third capacitive means for providing capacitance; and
switching means for selectively switching connections among said capacitive means and between said capacitive means and a reference voltage during first, second, and third periods,
wherein said switching means charges said first capacitive means to a first voltage level during said first period, said second capacitive means to a second voltage level during said second period, and said third capacitive means to a third voltage level during said third period, and wherein said third voltage level is greater than said second voltage level and said second voltage level is greater than said first voltage level.
18. The three-phase voltage tripler of claim 17 wherein said first voltage level is approximately equal to said reference voltage, said second voltage level is approximately equal to two times said first voltage level, and said third voltage is approximately equal to three times said first voltage level.
19. The three-phase voltage tripler of claim 17 wherein said switching means comprises:
a plurality of switches; and
clock means for generating clock signals that selectively control said plurality of switches.
20. The three-phase voltage tripler of claim 19 wherein said plurality of switches comprise:
a first transistor having a first terminal that communicates with said reference voltage, a control terminal, and a second terminal that communicates with a first end of said first capacitive means;
a second transistor having a first terminal that communicates with said second terminal of said first transistor, a control terminal, and a second terminal that communicates with a first end of said second capacitive means;
a third transistor having a first terminal that communicates with said second terminal of said second transistor, a control terminal, and a second terminal that communicates with a first end of said third capacitive means,
wherein said clock means selectively biases said first, second, and third transistors during said first, second, and third periods.
21. The three-phase voltage tripler of claim 17 wherein substantially the same peak current is drawn during said first, second, and third periods from a source of said reference voltage when said three-phase voltage tripler supplies a predetermined load current.
22. The three-phase voltage tripler of claim 17 wherein during said first period, a first end of said first capacitive means communicates with said reference voltage and a second end of said first capacitive means communicates with a common voltage.
23. The three-phase voltage tripler of claim 22 wherein during said second period, said first end of said first capacitive means communicates with a first end of said second capacitive means, said second end of said first capacitive means communicates with said reference voltage, and a second end of said second capacitive means communicates with said common voltage.
24. The three-phase voltage tripler of claim 23 wherein during said third period, said first end of said second capacitive means communicates with a first end of said third capacitive means, said second end of said second capacitive means communicates with said reference voltage, and a second end of said third capacitive means communicates with said common voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A process for age-hardening of a superalloy comprising the following steps:
i. treating the superalloy in solution;
ii. one-dimensional quenching the superalloy in oil; and
iii. rapid induction aging of the superalloy.
2. A process for age-hardening of a superalloy according to claim 1, wherein the superalloy is a nickel-base superalloy.
3. A process for age-hardening of a superalloy according to claim 2, wherein the superalloy is treated in solution for 2 hours at a temperature of about 1125 C.
4. A process for age-hardening of a superalloy according to claim 1 wherein the superalloy is one-dimentionally quenched in oil to room temperature.
5. A process for age-hardening of a superalloy according to claim 1, wherein the rapid induction aging includes placing the superalloy in a controlled Argon atmosphere medium-frequency induction furnace.
6. A process for age-hardening of a superalloy according to claim 5, wherein the rapid induction aging superalloy is in a controlled atmosphere at a temperature in the range of 750 C. to 800 C. for between 2 and 15 minutes.
7. A process for age-hardening of a nickel-base superalloy comprising the following steps:
i. treating the nickel-base superalloy in solution for 2 hours at about 1125 C.;
ii. one-dimensional quenching the nickel-base superalloy in oil to room temperature; and
iii. rapid induction aging of the nickel-base superalloy in a controlled Argon atmosphere medium-frequency induction furnace in the range of 750 C. to 800 C. for between 2 and 15 minutes.
8. A superalloy manufactured by the process according to claim 1.
9. A nickel-base superalloy manufactured by the process according to claim 1.
10. A nickel-base superalloy manufactured by the process according to claim 7.