What is claimed is:
1. A method for forming a non volatile memory on a silicon substrate having an existing topography, comprising the steps of:
forming a planarized isolation layer on the existing topography of the substrate, wherein the planarized isolation layer includes a top surface;
removing a portion of the planarized isolation layer to form walls extending from the top surface of the planarized isolation layer to the existing topography of the substrate;
forming a gate oxide region layer on and conforming to the existing topography of the substrate;
forming a conductive bottom plate layer on and conforming to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide region layer;
forming a dielectric layer on and conforming to the conductive bottom plate layer; and
forming a conductive top plate layer on and conforming to the dielectric layer.
2. The method of claim 1, wherein the step of forming a gate oxide region layer includes the step of thermally oxidizing the substrate to form the desired gate oxide thickness.
3. The method of claim 1, wherein the walls are substantially cylindrical in shape.
4. The method of claim 3, wherein the step of forming the gate oxide region includes the step of forming the gate oxide region to a thickness of less than 150 angstroms;
5. The method of claim 1, wherein the step of forming the planarized isolation layer includes the steps of:
forming a first masking layer over and upon the existing topography of the substrate;
depositing a layer of tetraethoxysilane (TEOS); and
planarizing the isolation layer using chemical mechanical polishing.
6. The method of claim 5, wherein the step of forming a first masking layer comprises the step of forming the masking layer of silicon nitride.
7. The method of claim 1, wherein the steps of forming a planarization isolation layer includes the step of depositing a layer of tetraethoxysilane (TEOS) through chemical vapor deposition (CVD).
8. The method of claim 5, wherein the step of removing a portion of the planarized isolation layer includes the steps of:
using a dry etch process to remove portions of the layer of tetraethoxysilane (TEOS);
using a wet etch process to remove portions of the masking layer.
9. The method of claim 1, wherein the step of forming a conductive bottom plate layer comprises the step of forming a layer of polysilicon.
10. The method of claim 1 wherein the step of forming a dielectric layer comprises the step of forming the dielectric from layers of silicon oxide, silicon nitride and silicon oxide (ONO).
11. The method of claim 1, wherein the conductive top plate layer comprises polysilicon.
12. The method of claim 5, wherein the step of removing a portion of the planarized isolation layer includes the step of using a dry etch process to remove portions of the layer of tetraethoxysilane and the masking layer.
13. A method for forming a non volatile memory array on a silicon substrate having an existing topography, comprising the steps of:
forming a floating gate tunneling oxide transistor (FLOTOX), including forming a first and second sourcedrain regions and a body region, and forming a floating gate, and wherein the step of forming the floating gate includes the steps of:
forming a planarized isolation layer on the gate oxide layer having a top surface;
removing a portion of the planarized isolation layer to form walls extending from the top surface of the planarized isolation layer to the existing topography of the substrate;
forming a gate oxide region layer on and conforming to the existing topography of the substrate;
forming the floating gate on and conforming to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide layer, and wherein the step of forming the floating gate includes the steps of:
forming a dielectric layer on and conforming to the floating gate; and
forming a control gate, wherein forming the control gate comprises forming the control gate on and conforming to the dielectric layer;
forming a wordline, including coupling the wordline to the control gate;
forming a bit line, including coupling the bit line to the second sourcedrain region; and
forming a source line, including coupling the source line to the first sourcedrain region.
14. The method of claim 13, wherein the step of forming a floating gate comprises the step of forming a polysilicon layer.
15. The method of claim 13, wherein the step of forming a dielectric layer comprises the step of forming layers of silicon oxide, silicon nitride and silicon oxide (ONO).
16. The method of claim 13, wherein the step of forming a control gate comprises the step of forming a polysilicon layer.
17. The method of claim 13, wherein the step of forming a gate oxide region includes the step of forming the gate oxide region to a thickness of less than 150 Angstroms.
18. A non volatile memory cell structure on a silicon substrate having an existing topography, comprising;
a gate oxide region layer on and conforming to the existing topography of the substrate;
a planarized isolation layer surrounding gate oxide region layer having a top surface;
an opening extending from the top surface of the planarized isolation layer to the gate oxide region and defined by walls interior to the planarized isolation layer;
a conductive bottom plate layer on and conforming to the top surface of the planarized isolation layer, the interior walls of the planarized isolation layer, and the gate oxide region;
a dielectric layer on and conforming to the conductive bottom plate layer; and
a conductive top plate layer on and conforming to the dielectric layer.
19. The non volatile memory cell structure of claim 18, wherein the interior walls of the planarized isolation layer, extending from the top surface of the planarized isolation layer to the gate oxide region, are substantially cylindrical in shape.
20. The non volatile memory cell structure of claim 18, wherein the gate oxide region has a thickness of less than 150 Angstroms.
21. The non volatile memory cell structure of claim 18, wherein the planarized isolation layer comprises a masking layer and an oxide layer.
22. The non volatile memory cell structure of claim 21, wherein the masking layer comprises silicon nitride.
23. The non volatile memory cell structure of claim 18, wherein the 20 planarization isolation layer comprises tetraethoxysilane (TEOS).
24. The non volatile memory cell structure of claim 18, wherein the conductive bottom plate layer comprises polysilicon, and wherein the conductive bottom plate layer serves as a floating gate.
25. The non volatile memory cell structure of claim 18, wherein the dielectric layer comprises layers of silicon oxide, silicon nitride and silicon oxide (ONO).
26. A non volatile memory cell array structure on a silicon substrate having an existing topography, comprising:
a plurality of floating gate tunneling oxide transistors (FLOTOX) located on the substrate’s existing topography, wherein each FLOTOX comprises:
a first and second sourcedrain region;
a body region;
a gate oxide region layer on and conforming to the body region;
a planarized isolation layer surrounding the gate oxide region layer and having a top surface;
an opening extending from the top surface of the planarized isolation layer to the gate oxide region and defined by walls interior to the planarized isolation layer;
a floating gate on and conforming to the top surface of the planarized isolation layer, the walls of the isolation layer, and the gate oxide layer;
a dielectric layer located on and conforming to the floating gate; and
a control gate is located on and conforms to the dielectric layer;
a wordline, wherein the wordline couples to the control gate;
a bit line, wherein the bit line couples to the second sourcedrain region; and
a source line, wherein the source line couples to the first sourcedrain region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Method for scanning, in particular documents, using a camera (K), an image sequence or a sequence of partial images being combined into a final image, in which a reference model (F) is projected onto the visual field of the camera, and
in which representational differences of different images are compensated on the basis of the geometrical information of the model (F).
2. Mobile telephone (MT) with a camera (K) and with an image processing device for generating a final image from the images or partial images obtained during a scanning process, characterized by
a projection device (L), by means of which a reference model (F) can be projected onto the visual field of the camera, and means of compensating for representational differences of the different images on the basis of the geometrical information of the model (F).