1. A bit line driver for a static random access memory (SRAM) cell comprising:
a first voltage supply for supplying a first voltage;
a second voltage supply for supplying a second voltage that is less than the first voltage;
a write circuit configured to drive a bit line and an inverse bit line when writing to the SRAM cell; and
a pre-charge circuit configured to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell,
wherein the bit line driver is configured to supply a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
2. The bit line driver of claim 1,
wherein the write circuit is configured to supply the voltage less than the first voltage by the threshold voltage of one transistor to the bit line when the write circuit drives the bit line to the high state, and
wherein the write circuit is configured to supply the voltage less than the first voltage by the threshold voltage of one transistor to the inverse bit line when the write circuit drives the inverse bit line to the high state.
3. The bit line driver of claim 2,
wherein the write circuit comprises:
a pair of pull-up circuits;
a pair of pull-down circuits each having a gate cross-coupled with a gate of an opposite side pull-up circuit of the pair of pull-up circuits; and
a pair of access circuits each interposed between a corresponding one of the pull-up circuits and a same-side pull-down circuit of the pair of pull-down circuits, and
wherein the write circuit is configured to selectively pull-up or pull-down the bit line and the inverse bit line according to a data signal and a write signal.
4. The bit line driver of claim 3,
wherein the pair of pull up circuits comprises:
a first transistor coupled between the first voltage supply and the bit line; and
a second transistor coupled between the first voltage supply and the inverse bit line,
wherein the pair of pull down circuits comprises:
a third transistor coupled between the second voltage supply and the bit line; and
a fourth transistor coupled between the second voltage supply and the inverse bit line, and
wherein the pair of access circuits comprises:
a fifth transistor interposed between the first transistor and the bit line;
a sixth transistor interposed between the second transistor and the inverse bit line;
a seventh transistor interposed between the third transistor and the bit line; and
an eighth transistor interposed between the fourth transistor and the inverse bit line.
5. The bit line driver of claim 4,
wherein the first transistor and the fourth transistor are configured to be turned on and off together,
wherein the second transistor and the third transistor are configured to be turned on and off together, and
wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are configured to be turned on and off together.
6. The bit line driver of claim 5,
wherein the first transistor and fourth transistor are configured to be turned on and off according to the data signal,
wherein the second transistor and the third transistor are configured to be turned on and off according to an inverse data signal, which is the inverse of the data signal; and
wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are configured to be turned on and off according to the write signal.
7. The bit line driver of claim 4,
wherein at least one of the first transistor and the third transistor and at least one of the second transistor and the fourth transistor are a same type of transistor as a row access transistor of the SRAM cell.
8. The bit line driver of claim 4,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-type transistors.
9. The bit line driver of claim 4,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the eighth transistor are n-type transistors, and
wherein the fifth transistor and the sixth transistor are p-type transistors.
10. The bit line driver of claim 1,
wherein the pre-charge circuit is configured to supply the voltage less than the first voltage by the threshold voltage of one transistor to the bit line when the pre-charge circuit drives the bit line to the high state, and
wherein the pre-charge circuit is configured to supply the voltage less than the first voltage by the threshold voltage of one transistor to the inverse bit line when the pre-charge circuit drives the inverse bit line to the high state.
11. The bit line driver of claim 10,
wherein the pre-charge circuit comprises:
a first pull-up circuit configured to pull-up the bit line to the voltage less than the first voltage by the threshold voltage of one transistor according to a pre-charge signal;
a second pull-up circuit configured to pull-up the inverse bit line to the voltage less than the first voltage by the threshold voltage of one transistor according to the pre-charge signal; and
a balancing circuit configured to balance a voltage of the bit line with a voltage of the inverse bit line according to an inverse pre-charge signal.
12. The bit line driver of claim 11,
wherein the first pull-up circuit comprises a first transistor interposed between the first voltage supply and the bit line,
wherein the second pull-up circuit comprises a second transistor interposed between the first voltage supply and the inverse bit line, and
wherein the balancing circuit comprises a third transistor coupled between the bit line and the inverse bit line.
13. The bit line driver of claim 12,
wherein the first transistor and the second transistor are a same type of transistor as a row access transistor of the SRAM cell.
14. The bit line driver of claim 12,
wherein the first transistor and the second transistor are n-type transistors and the third transistor is a p-type transistor.
15. A static random access memory (SRAM) array comprising:
a plurality of word lines arranged in rows, each of the word lines for supplying a corresponding one of a plurality of word signals;
a plurality of bit lines arranged in columns, each of the bit lines for supplying a corresponding one of a plurality of bit signals;
a plurality of inverse bit lines arranged with the bit lines in columns, each of the inverse bit lines for supplying a corresponding one of a plurality of inverse bit signals that is the inverse of the bit signal supplied by the corresponding one of the bit lines in a same column;
a first voltage supply for supplying a first voltage;
a second voltage supply for supplying a second voltage that is less than the first voltage;
a plurality of SRAM cells arranged in rows and columns, each of the SRAM cells corresponding to one of each of the word lines, the bit lines, and the inverse bit lines;
a word line driver configured to drive the word lines; and
a bit line driver configured to drive the bit lines and the inverse bit lines,
wherein the bit line driver is configured to supply a voltage less than the first voltage by a threshold voltage of one transistor of the bit line driver to the one of the bit lines when the bit line driver drives one of the bit lines to a high state, and
wherein the bit line driver is configured to supply the voltage less than the first voltage by a threshold voltage of one transistor of the bit line driver to the one of the inverse bit lines when the bit line driver drives one of the inverse bit lines to the high state.
16. The SRAM array of claim 15,
wherein the bit line driver comprises a plurality of write circuits, each of the write circuits corresponding to a bit line of the bit lines, an inverse bit line of the inverse bit lines, and a column of the SRAM cells,
wherein each of the write circuits comprises:
a pair of pull-up circuits;
a pair of pull-down circuits each having a gate cross-coupled with a gate of an opposite side pull-up circuit of the pair of pull-up circuits; and
a pair of access circuits each interposed between a corresponding one of the pull-up circuits and a same-side pull-down circuit of the pair of pull-down circuits, and
wherein each of the write circuits is configured to selectively pull-up or pull-down the bit line and the inverse bit line according to a data signal and a write signal.
17. The SRAM array of claim 16,
wherein the pair of pull-up circuits comprise n-type transistors.
18. The SRAM array of claim 15,
wherein the bit line driver comprises a plurality of pre-charge circuits, each of the pre-charge circuits corresponding to a bit line of the bit lines, an inverse bit line of the inverse bit lines, and a column of the SRAM cells, and
wherein each of the pre-charge circuits comprises:
a first pull-up circuit configured to pull-up the bit line to the voltage less than the first voltage by the threshold voltage of one transistor according to a pre-charge signal;
a second pull-up circuit configured to pull-up the inverse bit line to the voltage less than the first voltage by the threshold voltage of one transistor according to the pre-charge signal; and
a balancing circuit configured to balance a voltage of the bit line with a voltage of the inverse bit line according to an inverse pre-charge signal.
19. The SRAM array of claim 18,
wherein the first pull-up circuit and the second pull-up circuit comprise n-type transistors.
20. The SRAM array of claim 15,
wherein each of the SRAM cells comprises:
a first transistor comprising:
a gate coupled to the corresponding word line;
a source coupled to the corresponding inverse bit line; and
a drain;
a second transistor comprising:
a gate coupled to the corresponding word line;
a source coupled to the corresponding bit line; and
a drain
a third transistor comprising:
a gate coupled to the drain of the second transistor;
a source coupled to the second voltage supply; and
a drain coupled to the drain of the first transistor;
a fourth transistor comprising:
a gate coupled to the drain of the first transistor;
a source coupled to the second voltage supply; and
a drain coupled to the drain of the second transistor;
a fifth transistor comprising:
a gate coupled to the drain of the second transistor;
a source coupled to the first voltage supply; and
a drain coupled to the drain of the first transistor; and
a sixth transistor comprising:
a gate coupled to the drain of the first transistor
a source coupled to the first voltage supply; and
a drain coupled to the drain of the second transistor,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-type transistors, and
wherein the fifth transistor and the sixth transistor are p-type transistors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A lightweight, wearable device comprising:
a radio frequency identification tag reader;
an external communication device that is structured and arranged to communicate with a remote server;
an alarm device that is adapted to generate at least one of a visual, an audible, and a haptic signal;
at least one data storing device for storing data and at least one of an application, an algorithm, and a driver program having multi-dimensional movement and acceleration data representative of hand-washing activity;
an accelerometer that is structured and arranged to measure multi-dimensional movement and acceleration of the device;
a processing device that is in communication with the radio frequency identification tag reader, the external communication device, the alarm device, the at least one data storing device, and the accelerometer, the processing device being adapted to call and execute an appropriate at least one application, algorithm, and driver program that uses measured multi-dimensional movement and acceleration data to evaluate hand-washing activity; and
a central housing portion into which components of the device are structured and arranged, the central housing portion being at least one of shockproof, watertight, and airtight,
the device useable in a method of monitoring an instance and a duration of hand-washing activity, the method comprising:
monitoring an environment for identification tag signals;
identifying a source of a monitored tag signal, the source taken from any of a plurality of dispensers, a plurality of directionally-controlled tags, and a plurality of unique passive radio frequency tags;
calling from a database and executing at least one of an application, an algorithm, and a driver program corresponding to the identified signal source;
measuring movement and acceleration of the wearable device;
determining when hand-washing activity has begun by comparing measured movement and acceleration data to data providing indicia of hand-washing activity stored in a corresponding database;
determining when hand-washing activity has ceased by comparing measured movement and acceleration data to the data providing indicia of hand-washing activity;
calculating a duration of hand-washing activity;
comparing the duration of hand-washing activity to a pre-determined minimum handwashing requirement, to determine whether or not said hand-washing activity complies with the minimum hand-washing requirements;
calculating a duration of time between a most recent hand-washing activity and at least one of an entry time into a zone or room and an opening time of a medical supply or medical device;
determining whether or not the duration of time is less than or equal to a pre-established threshold time; and
alerting a wearer of the wearable device to perform remedial hand-washing activity if said duration of time is less than the pre-established threshold time.
2. The device as recited in claim 1 further comprising a gyroscope that is structured and arranged to measure multi-dimensional movement and moment of the device, and wherein the processing device is adapted to call and execute an appropriate at least one application, algorithm, and driver program that uses measured multi-dimensional movement and moment data to evaluate hand-washing activity.
3. The device as recited in claim 1, wherein the wearable device has at least one of the following properties:
weighs between one (1) and four (4) ounces;
has a thickness of approximately 0.5 inches; and
has a width between 0.5 inches and one (1) inch.
4. The device as recited in claim 3, wherein the wearable device has at least one of the following properties:
weighs approximately two (2) ounces; and
has a width of approximately 0.8 inches.
5. The device as recited in claim 1, wherein the wearable device is selected from a group consisting of:
a wristband device;
a ring; and
an armband device.
6. The device as recited in claim 1 further comprising:
a cover portion that is structured and arranged to encase or substantially encase the central housing portion; and
an attaching portion that is fixedly attached to or integrated into the cover portion for releasably securing the device at or near a wearer’s wrist.
7. The device as recited in claim 1 further comprising a power supply device having a wireless charging component.
8. The method as recited in claim 1, wherein the minimum hand-washing requirements are provided in guidelines that are stored in an appropriate database.
9. The method as recited in claim 8, wherein the guidelines are World Health Organization guidelines for hand hygiene.
10. The method as recited in claim 1 further comprising generating a continuous alarm signal until said remedial hand-washing activity complies with the minimum hand-washing requirements.
11. The method as recited in claim 1 further comprising:
generating a signal of noncompliance if said duration is less than the pre-established threshold time; and
recording in the data storing device of the wearable device a date and time of the noncompliance signal.
12. The method as recited in claim 11, further comprising:
determining when a remedial hand-washing activity has begun by comparing measured movement and acceleration data to data providing indicia of hand-washing activity stored in a corresponding database;
determining when the remedial hand-washing activity has ceased by comparing measured movement and acceleration data to the data providing indicia of hand-washing activity;
calculating a duration of remedial hand-washing activity; and
comparing the duration of re-medial hand-washing activity to the pre-determined minimum hand-washing requirements, to determine whether or not said remedial hand-washing activity complies with the minimum hand-washing requirements.
13. The method as recited in claim 12 further comprising generating a continuous alarm signal until said remedial hand-washing activity complies with the minimum hand-washing requirements.
14. The method as recited in claim 1, the wearable device further including a gyroscope that is structured and arranged to measure multi-dimensional movement and moment of the device, the method further comprising:
measuring movement and moment of the wearable device;
determining when hand-washing activity has begun by comparing measured movement and moment data to data providing indicia of hand-washing activity stored in a corresponding database;
determining when hand-washing activity has ceased by comparing measured movement and moment to the data providing indicia of hand-washing activity;
calculating a duration of hand-washing activity therefrom; and
comparing the duration of hand-washing activity to a pre-determined minimum hand-washing requirement, to determine whether or not said hand-washing activity complies with the minimum hand-washing requirements.
15. The method as recited in claim 1 further comprising:
identifying a wearer of the wearable device; and
attributing any hand-washing activity of the wearer to a database unique to the corresponding wearer.
16. The method as recited in claim 1 further comprising generating a signal to notify the wearer that movement and acceleration data are being recorded.