1. An amplifier comprising:
an amplifier stage having an input terminal and an output terminal; and
an active inductor comprising:
a first resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal;
a second resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the first resistor, a control electrode coupled to receive a bias voltage, and a second current electrode; and <a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the second terminal of the second resistor, and a second current electrode coupled to a first power supply voltage terminal.
2. The amplifier of claim 1, wherein a transconductance of the first transistor is substantially equal to a transconductance of the second transistor.
3. The amplifier of claim 2, wherein the transconductance of the first and second transistors is at least partially determined by a transistor channel width to length ratio of the first and second transistors.
4. The amplifier of claim 1, wherein a voltage gain of the active inductor is substantially independent of a transconductance of the first and second transistors.
5. The amplifier of claim 1, wherein the first and second resistors are implemented using polysilicon on an integrated circuit.
6. The amplifier of claim 1, wherein a first resistance value of the first resistor at least partially determines a first voltage gain of the amplifier for a first predetermined frequency, and a second resistance value of the second resistor at least partially determines a second voltage gain of the amplifier for a second predetermined frequency, wherein the second predetermined frequency is higher than the first predetermined frequency.
7. The amplifier of claim 1, wherein the amplifier stage comprises:
a third resistor having a first terminal coupled to a second power supply voltage terminal, and a second terminal coupled to the output terminal of the amplifier stage; and
a third transistor having a first current electrode coupled to the second terminal of the third resistor, a control electrode for receiving an input signal, and a second current electrode coupled to the first power supply voltage terminal.
8. The amplifier of claim 7, wherein the amplifier stage further comprises:
a fourth resistor having a first terminal coupled to the second power supply voltage terminal, and a second terminal; and
a fourth transistor having a first current electrode coupled to second terminal of the fourth resistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the first power supply voltage terminal.
9. The amplifier of claim 8, wherein the active inductor further comprises:
a fifth resistor having a first terminal coupled to the second power supply voltage terminal, and a second terminal coupled to the first current electrode of the first transistor;
a sixth resistor having a first terminal coupled to the second power supply voltage terminal, and a second terminal;
a seventh resistor having a first terminal coupled to the second terminal of the sixth resistor, and a second terminal coupled to the second terminal of the fourth resistor;
an eighth resistor having a first terminal coupled to the second terminal of the fourth resistor, and a second terminal;
a fifth transistor having a first current electrode coupled to the second terminal of the sixth resistor, a control electrode coupled to the second power supply voltage terminal, and a second current electrode; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the second terminal of the eighth resistor, and a second current electrode coupled to the first power supply voltage terminal.
10. The amplifier of claim 1, wherein the first and second transistors are characterized as being metal-oxide semiconductor (MOS) transistors and an inductor value of the active inductor is substantially equal to a gate-to-source parasitic capacitance of the second transistor multiplied by a resistance value of the second resistor.
11. The amplifier of claim 1, wherein the input terminal is for receiving a low voltage digital signal (LVDS) from a radio frequency front-end of a cellular handset.
12. An amplifier comprising:
an amplifier stage having an input terminal and an output terminal, the amplifier stage comprising:
a first resistor having a first terminal coupled to a first power supply voltage terminal, and a second terminal coupled to the output terminal of the amplifier stage; and
a first transistor having a first current electrode coupled to the second terminal of the first resistor, a control electrode for receiving an input signal, and a second current electrode coupled to a second power supply voltage terminal; and
an active inductor comprising:
a second resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal;
a third resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal;
a second transistor having a first current electrode coupled to the second terminal of the second resistor, a control electrode coupled to receive a bias voltage, and a second current electrode; and
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the second terminal of the third resistor, and a second current electrode coupled to the second power supply voltage terminal.
13. The amplifier of claim 12, wherein the bias voltage is equal to a power supply voltage provided to the first power supply voltage terminal.
14. The amplifier of claim 12, wherein a transconductance of the second and third transistors is at least partially determined by a transistor channel width to length ratio of the second and third transistors.
15. The amplifier of claim 12, wherein a voltage gain of the active inductor is substantially independent of a transconductance of the second and third transistors.
16. The amplifier of claim 12, wherein a first resistance value of the second resistor at least partially determines a first voltage gain of the amplifier for a first predetermined frequency, and a second resistance value of the third resistor at least partially determines a second voltage gain of the amplifier for a second predetermined frequency, wherein the second predetermined frequency is higher than the first predetermined frequency.
17. The amplifier of claim 12, wherein the amplifier stage is a differential amplifier further comprising:
a fourth resistor having a first terminal coupled to the first power supply voltage terminal, and a second terminal for providing a second output terminal of the amplifier stage; and
a fourth transistor having a first current electrode coupled to the second terminal of the fourth resistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the second power supply voltage terminal.
18. An amplifier comprising:
an amplifier stage having an input terminal and an output terminal, the amplifier stage comprising:
a first resistor having a first terminal coupled to a first power supply voltage terminal, and a second terminal coupled to the output terminal of the amplifier stage;
a first transistor having a first current electrode coupled to the second terminal of the first resistor, a control electrode for receiving an input signal, and a second current electrode; and
a first current source having a first terminal coupled to the second current electrode of the first transistor and a second terminal coupled to a second power supply voltage terminal; and
an active inductor comprising:
a second resistor having a first terminal coupled to the first power supply voltage terminal, and a second terminal;
a third resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal coupled to the second terminal of the second resistor;
a fourth resistor having a first terminal coupled to the output terminal of the amplifier stage, and a second terminal;
a second transistor having a first current electrode coupled to the second terminal of the second and third resistors, a control electrode coupled to receive a bias voltage, and a second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the second terminal of the fourth resistor, and a second current electrode; and
a second current source having a first terminal coupled to the second current electrode of the third transistor, and a second terminal coupled to the second power supply voltage terminal.
19. The amplifier of claim 18, further comprising:
a fifth resistor having a first terminal coupled to the first power supply voltage terminal, and a second terminal for providing a second output terminal of the amplifier stage;
a fourth transistor having a first current electrode coupled to the second terminal of the fifth resistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the first terminal of the first current source;
a sixth resistor having a first terminal coupled to the first power supply voltage terminal, and a second terminal;
a seventh resistor having a first terminal coupled to the second terminal of the sixth resistor, and a second terminal coupled to the second output terminal of the amplifier stage;
an eighth resistor having a first terminal coupled to the second terminal of the seventh resistor, and a second terminal;
a fifth transistor having a first current electrode coupled to the second terminal of the sixth resistor, a control electrode coupled to receive the bias voltage, and a second current electrode; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the second terminal of the eighth resistor, and a second current electrode coupled to the first terminal of the second current source.
20. The amplifier of claim 19, wherein the input signal and the second input signal are together characterized as being a differential low voltage digital signal (LVDS) from a radio frequency (RF) front-end of a cellular handset.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A reflective diffraction grating device on a planar waveguide platform for use in demultiplexing an optical signal, comprising:
an input port for launching a beam of light comprising a plurality of wavelength channels, defined by an average wavelength, at a small diffraction grating incident angle;
a reflective diffraction grating for dispersing the wavelength channels at various angles according to wavelength, the reflective diffraction grating having a plurality of substantially triangular steps, each step comprising a reflective wall defined by a facet length, and a sidewall defined by a sidewall length; and
a plurality of output ports positioned to capture the wavelength channels;
wherein an aspect ratio, defined by the facet length divided by the sidewall length, is greater than 3.
2. The device according to claim 1, wherein the aspect ratio is greater than 5.
3. The device according to claim 1, wherein the aspect ratio is greater than 10.
4. The device according to claim 3, wherein the diffraction grating incident angle is less than 6\xb0.
5. The device according to claim 3, wherein the sidewall length is less than or equal to two times the average wavelength.
6. The device according to claim 1, wherein the sidewall length is less than or equal to the average wavelength.
7. The device according to claim 1, wherein the incidence angle less than 30\xb0.
8. The device according to claim 1, wherein the incidence angle is less than 15\xb0.
9. The device according to claim 1, wherein the facet length is greater than 5 \u03bcm; and wherein the sidewall length is less than 3000 nm.
10. The device according to claim 1, wherein the sidewall length is less than 1550 nm.
11. The device according to claim 1, wherein the incidence angle is less than 45\xb0.
12. A reflective diffraction grating device on a planar waveguide platform for use in multiplexing or demultiplexing optical channels defined by an average wavelength, comprising:
a reflective diffraction grating including a plurality of substantially triangular steps, each step comprising:
a reflective wall defined by a facet length; and
a non-reflecting sidewall defined by a sidewall length;
an input port for launching a beam of light comprising the optical channels at the diffraction grating at a small incident angle;
a first output port for outputting one of the optical channels; and
a second output port for outputting another of the optical channels;
wherein the facet length and the incident angle are selected to ensure that the grating provides diffraction in an order with an absolute value of 7 or less.
13. The device according to claim 12, wherein the order is 5 or less.
14. The device according to claim 12, wherein the order is 3 or less.
15. The device according to claim 14, wherein the diffraction grating incident angle is less than 6\xb0.
16. The device according to claim 15, wherein the sidewall length is less than or equal to the average wavelength.
17. The device according to claim 12, wherein the incidence angle is less than 45\xb0.
18. The device according to claim 12, wherein the incidence angle less than 30\xb0.
19. The device according to claim 12, wherein the incidence angle is less than 15\xb0.
20. The device according to claim 12, wherein the sidewall length is less than or equal to two times the average wavelength.
21. The device according to claim 12, wherein the sidewall length is less than or equal to the average wavelength.
22. The device according to claim 12, wherein the facet length is greater than 5 \u03bcm; and wherein the sidewall length is less than 3000 nm.
23. The device according to claim 12, wherein the sidewall length is less than 1550 nm.
24. A reflective diffraction grating device on a planar waveguide platform for use in demultiplexing an optical signal, comprising:
an input port for launching a beam of light comprising a plurality of wavelength channels, defined by an average wavelength, at a small diffraction grating incident angle;
a reflective diffraction grating for dispersing the wavelength channels at various angles according to wavelength, the reflective diffraction grating having a plurality of steps defining substantially triangular grooves, each step comprising a reflective wall defined by a facet length, and a sidewall defined by a sidewall length; and
a plurality of output ports positioned to capture the wavelength channels;
wherein the sidewall length is less than or equal to twice the average wavelength.
25. The device according to claim 24, wherein the sidewall length is less than or equal to the average wavelength.
26. The device according to claim 24, wherein the sidewall length is less than 3000 nm.
27. The device according to claim 24, wherein the incidence angle is less than 1500 nm.
28. The device according to claim 24, wherein the incidence angle less than 45\xb0.
29. The device according to claim 24, wherein the incidence angle less than 30\xb0.
30. The device according to claim 24, wherein the incidence angle is less than 15\xb0.
31. A reflective diffraction grating device on a planar waveguide platform for use in demultiplexing an optical signal, comprising:
an input port for launching a beam of light comprising a plurality of wavelength channels, defined by an average wavelength, at a diffraction grating incident angle;
a reflective diffraction grating for dispersing the wavelength channels at various angles according to wavelength, the reflective diffraction grating having a plurality of steps defining substantially triangular grooves, each step comprising a reflective wall defined by a facet length, and a sidewall defined by a sidewall length; and
a plurality of output ports positioned to capture the wavelength channels; wherein the sidewall length is less than or equal to twice the average wavelength; and
wherein the facet length is greater than 5 \u03bcm.
32. The device according to claim 31, wherein the sidewall length is less than 1550 nm.
33. The device according to claim 31, wherein the incidence angle is less than 45\xb0.