1. A semiconductor memory device comprising:
a transistor formed in a surface region of a semiconductor substrate, and having a gate electrode and sourcedrain regions;
a capacitor formed above the transistor, and selected by the transistor, the capacitor having a first electrode, a second electrode, and a dielectric film formed between the first and second electrodes;
a first contact formed on a side surface portion of the capacitor so as to be close to at least a portion of the capacitor, the first contact being connected to one of the sourcedrain regions; and
a sidewall insulating film formed, in contact with at least the capacitor, on sidewalls of the first contact.
2. A device according to claim 1, wherein the insulating film extends downward from the side surface portion of the capacitor.
3. A device according to claim 1, further comprising:
a second contact connected to the first electrode and the other one of the sourcedrain regions;
a third contact formed on the second electrode; and
an interconnection which connects the first and third contacts.
4. A device according to claim 1, wherein the second contact is offset from the capacitor.
5. A device according to claim 1, wherein the dielectric film is a ferroelectric film.
6. A semiconductor memory device comprising:
a transistor formed in a surface region of a semiconductor substrate, and having a gate electrode and sourcedrain regions;
a capacitor formed above the transistor, having a first electrode, a second electrode, and a dielectric film formed between the first and second electrodes, and selected by the transistor;
an insulating film formed on a side surface portion of the capacitor; and
a first contact formed on the side surface portion of the capacitor so as to be partially in contact with the insulating film, and connected to one of the sourcedrain regions.
7. A device according to claim 6, further comprising:
a second contact connected to the first electrode and the other one of the sourcedrain regions;
a third contact formed on the second electrode; and
an interconnection which connects the first and third contacts.
8. A device according to claim 6, wherein the dielectric film is a ferroelectric film.
9. A semiconductor memory device fabrication method comprising:
forming a transistor having a gate electrode and sourcedrain regions in a surface region of a semiconductor substrate;
forming, on the semiconductor substrate, a first insulating film which covers the transistor;
forming, in the first insulating film, a first contact connected to one of the sourcedrain regions;
forming a first electrode material, dielectric film, and second electrode material sequentially on the first insulating film;
etching the second electrode material, dielectric film, and first electrode material to form a capacitor having a first electrode, dielectric film, and second electrode;
forming, on the first insulating film, a second insulating film which covers the capacitor;
forming, in the second insulating film, a second contact connected to the second electrode;
forming, in the second insulating film, a hole which is in contact with at least a portion of the capacitor, the hole exposing the other one of the sourcedrain regions;
forming a third insulating film on inner side surfaces of the hole; and
forming, in the hole, a third contact connected to the other one of the sourcedrain regions.
10. A method according to claim 9, wherein the formation of the capacitor comprises:
etching the second electrode material and dielectric film; and
etching the first electrode material,
a size of the first electrode being larger than sizes of the second electrode material and dielectric film.
11. A method according to claim 9, wherein the formation of the hole comprises:
etching the second insulating film up to the second electrode; and
etching the second insulating film, second electrode, dielectric film, and first electrode.
12. A method according to claim 10, wherein the dielectric film is a ferroelectric film.
13. A semiconductor memory device fabrication method comprising:
forming a transistor having a gate electrode and sourcedrain regions in a surface region of a semiconductor substrate;
forming, on the semiconductor substrate, a first insulating film which covers the transistor;
forming, in the first insulating film, a first contact connected to one of the sourcedrain regions;
forming a first electrode material, dielectric film, and second electrode material sequentially on the first insulating film;
etching the second electrode material, dielectric film, and first electrode material to form a capacitor having a first electrode, dielectric film, and second electrode;
forming a second insulating film on a sidewall of the capacitor;
forming, on the first insulating film, a third insulating film which covers the capacitor;
forming, in the third insulating film, a second contact connected to the second electrode;
forming, in the first and third insulating films, a hole which is in contact with at least a portion of the capacitor, the hole exposing the other one of the sourcedrain regions; and
forming, in the hole, a third contact connected to the other one of the sourcedrain regions.
14. A method according to claim 13, wherein the dielectric film is a ferroelectric film.
15. A semiconductor memory device fabrication method comprising:
forming a transistor having a gate electrode and sourcedrain regions in a surface region of a semiconductor substrate;
forming, on the semiconductor substrate, a first insulating film which covers the transistor;
forming, in the first insulating film, a first contact connected to one of the sourcedrain regions;
forming a first electrode material, dielectric film, and second electrode material sequentially on the first insulating film;
etching the second electrode material, dielectric film, and first electrode material to form a capacitor having a first electrode, dielectric film, and second electrode;
forming, on the first insulating film, a second insulating film which covers the capacitor;
forming, in the second insulating film, a second contact connected to the second electrode;
forming, in the first and third insulating films, a hole which is in contact with a sidewall of the capacitor, the hole exposing the other one of the sourcedrain regions;
forming an insulating portion by oxidizing the sidewall of the capacitor from the hole; and
forming, in the hole, a third contact connected to the other one of the sourcedrain regions.
16. A method according to claim 15, wherein the dielectric film is a ferroelectric film.
17. A semiconductor memory device fabrication method comprising:
forming a transistor having a gate electrode and sourcedrain regions in a surface region of a semiconductor substrate;
forming, on the semiconductor substrate, a first insulating film which covers the transistor;
forming, in the first insulating film, a first contact connected to one of the sourcedrain regions;
forming a second insulating film on the first insulating film;
forming, in the first and second insulating films, a second contact connected to the other one of the sourcedrain regions;
forming a first electrode material, electric film, and second electrode material sequentially on the second insulating film;
etching the second electrode material, dielectric film, and first electrode material to form a capacitor having a first electrode, dielectric film, and second electrode;
forming, on the second insulating film, a third insulating film which covers the capacitor;
forming, in the third insulating film, a third contact connected to the second electrode;
forming, in the second and third insulating films, a hole which is in contact with a sidewall of the capacitor, the hole exposing the other one of the sourcedrain regions;
forming a fourth insulating film on side surfaces of the hole; and
forming, in the hole, a fourth contact connected to the first contact.
18. A method according to claim 17, wherein the dielectric film is a ferroelectric film.
19. A semiconductor memory device fabrication method comprising:
forming a transistor having a gate electrode and sourcedrain regions in a surface region of a semiconductor substrate;
forming, on the semiconductor substrate, a first insulating film which covers the transistor;
forming, in the first insulating film, a first contact connected to one of the sourcedrain regions, and a second contact connected to the other one of the sourcedrain regions;
forming a first electrode material, dielectric film, and second electrode material sequentially on the first insulating film;
etching the second electrode material, dielectric film, and first electrode material to form a capacitor having a first electrode connected to the first contact, a dielectric film, and a second electrode;
forming, on the first insulating film, a second insulating film which covers the capacitor;
forming, in the second insulating film, a third contact connected to the second electrode;
forming, in the second insulating film, a hole which is in contact with a sidewall of the capacitor, the hole exposing an upper surface of the second contact;
forming a third insulating film on side surfaces of the hole; and
forming, in the hole, a fourth contact connected to the second contact.
20. A method according to claim 19, wherein the dielectric film is a ferroelectric film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for correcting at least one of pileup effects or charge sharing effects in multi-cell photon counting detectors, said method comprising:
determining a correction coefficient using a count rate of an entire spectrum; and
applying the determined correction to the counts recorded in an energy window of interest.
2. A method in accordance with claim 1 further comprising measuring a coincidence in adjacent cells, and reconstructing signal amplitudes of charge sharing events.
3. A method in accordance with claim 2 wherein said reconstruction further comprises summing signals from the coincident cells.
4. A method in accordance with claim 1 further comprising determining a detector response function for charge sharing.
5. A method in accordance with claim 4 wherein said determining a detector response function further comprises measuring detector response utilizing a monoenergetic beam of photons.
6. A method in accordance with claim 4 wherein said determining a detector response function further comprises modeling the response of the detector.
7. A method in accordance with claim 4 wherein said determining a detector response function further comprises a combination of measuring detector response utilizing a monoenergetic beam of photons and modeling the response of the detector.
8. A method in accordance with claim 1 further comprising:
determining a correction matrix for count loss;
truncating components of the correction matrix below a predetermined energy level to obtain a truncated correction matrix;
inverting the truncated correction matrix to obtain an inverse response matrix; and
applying the inverse response matrix to reconstruct a spectrum.
9. A method in accordance with claim 8 performed using a mammography imaging apparatus to image a human breast.
10. A method in accordance with claim 1 performed using a mammography imaging apparatus to image a human breast.
11. An apparatus for correcting at least one of pileup effects or charge sharing effects in multi-cell photon counting detectors, said apparatus configured to:
determine a correction coefficient using a count rate of an entire spectrum; and
apply the determined correction to the counts recorded in an energy window of interest.
12. An apparatus in accordance with claim 11 further configured to measure a coincidence in adjacent cells, and to reconstruct signal amplitudes of charge sharing events.
13. An apparatus in accordance with claim 12 wherein to reconstruct signal amplitudes of charge sharing events, said apparatus further configured to sum signals from the coincident cells.
14. An apparatus in accordance with claim 11 further configured to determine a detector response function for charge sharing.
15. An apparatus in accordance with claim 14 wherein to determine a detector response function, said apparatus further configured to measure detector response utilizing a monoenergetic beam of photons.
16. An apparatus in accordance with claim 11 further configured to:
determine a correction matrix for count loss;
truncate components of the correction matrix below a predetermined energy level to obtain a truncated correction matrix;
invert the truncated correction matrix to obtain an inverse response matrix; and
apply the inverse response matrix to reconstruct a spectrum.
17. An apparatus in accordance with claim 16 wherein the apparatus is a mammography imaging apparatus.
18. An apparatus in accordance with claim 11 wherein the apparatus is a mammography imaging apparatus.