1. A method for accessing system memory having one or more memory modules, comprising:
detecting defective memory locations of the memory modules;
storing information identifying the defective memory locations in one or more system memory defect tables; and
mapping the defective memory locations identified in the system memory defect tables to replacement memory locations, wherein the step of detecting comprises:
reducing a refresh rate for refreshing rows of memory cells below an operational refresh rate specified by a manufacture of the memory modules;
identifying as marginal, memory locations of the memory modules having memory cells that fail to maintain data at the reduced refresh rate; and
storing information identifying the marginal memory locations in the system memory defect tables.
2. The method of claim 1, further comprising maintaining the information in the system memory defect tables across reset cycles.
3. The method of claim 2, wherein maintaining the information in the system memory defect tables across reset cycles comprises storing the system memory defect tables in non-volatile memory.
4. The method of claim 3, wherein storing the system memory defect tables in non-volatile memory comprises storing the system memory defect tables in non-volatile memory located on the memory modules.
5. The method of claim 1, wherein the storing and mapping are performed by operating system code.
6. The method of claim 1, further comprising, avoiding use of a memory module if the total number of defective locations detected thereon exceeds a predetermined threshold amount.
7. The method of claim 1, wherein mapping the defective memory locations identified in the system memory defect tables to replacement memory locations comprises generating page table entries that map virtual addresses to physical addresses of the replacement memory locations.
8. A method for identifying marginal dynamic memory cells in one or more memory modules of system memory, comprising:
a) reducing a refresh rate for refreshing rows of memory cells in the memory cells to a level below an operational refresh rate specified by a manufacturer of the memory modules;
b) identifying as marginal, memory locations of the memory modules having memory cells that fail to maintain data at the reduced refresh rate;
c) storing information identifying the marginal memory locations in one or more system memory defect tables; and
d) mapping the marginal memory locations to replacement memory locations.
9. The method of claim 8, comprising:
repeating the operations of a) and b) to incrementally reduce the refresh rate and detecting marginal memory locations at incrementally reduced refresh rates.
10. The method of claim 8, wherein the operations a)-d) are performed by an operating system after a system reset.
11. The method of claim 8, further comprising maintaining information in the system memory defect tables across reset cycles.
12. A system, comprising:
one or more processing devices;
system memory addressable by the processing devices, the system memory including one or more memory modules;
one or more system memory defect tables; and
a component executable by one or more of the processing devices to detect defective memory locations of the memory modules, store information identifying the defective memory locations in one or more system memory defect tables, and map the defective memory locations identified in the system memory defect tables to replacement memory locations, the component being configured to identify memory locations as defective by reducing a refresh rate of the memory modules and storing information identifying defective memory locations having cells unable to maintain data at reduced refresh rates in the system memory defect tables including reducing the refresh rate to a level below an operational refresh rate specified by a manufacturer of the memory modules.
13. The system of claim 12, wherein information in the system memory defect tables is maintained across reset cycles of the system.
14. The system of claim 12, wherein the system memory defect tables are stored in non-volatile memory.
15. The system of claim 14, wherein the system memory defect tables are stored in non-volatile memory located on the memory modules.
16. The system of claim 15, wherein the system memory defect tables are stored in non-volatile memory located on the memory modules that are also used for serial presence detect (SPD) purposes.
17. The system of claim 12, wherein the component is configured to map the defective memory locations identified in the system memory defect tables to replacement memory locations by generating page table entries that map virtual addresses to physical addresses of the replacement memory locations.
18. The system of claim 12, wherein the component is configured to map defective memory locations of one memory module to replacement memory locations of another memory module.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An SRAM array comprising a plurality of SRAM cells, each of said SRAM cells comprising:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where at least two adjacent NFETs have a sourcedrain diffusion region and a leakage path diffusion region under the source drain diffusion region positioned between their respective body regions, wherein the sourcedrain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the sourcedrain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the sourcedrain diffusion but at relatively lower concentrations than the sourcedrain diffusion, thereby presenting a lower barrier to junction leakage than the sourcedrain regions.
2. The SRAM array of claim 1 where the leakage path diffusion region under the sourcedrain diffusion region is counter-doped with a different species than the sourcedrain diffusion region.
3. The SRAM array of claim 1, wherein each SRAM cell is a six-transistor CMOS SRAM cell, and where the body regions of the four NFETs of the six-transistor CMOS SRAM cell are all linked together with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
4. The SRAM array of claim 1, wherein one of the NFETs sharing the leakage path diffusion region is one of the pass gate NFETs and the other NFET sharing the leakage path diffusion region is one of the inverter NFETs.
5. The SRAM array of claim 1 wherein the NFETs are fabricated in (100) crystal orientation silicon regions.
6. The SRAM array of claim 1 wherein the PFETs are fabricated in (110) crystal orientation silicon regions.
7. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, each of the adjacent SRAM cells comprising:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least one of the NFETs from the first SRAM cell and at least one of the NFETs from the second SRAM cell share a leakage path between body regions, the respective NFETs sharing a leakage path being adjacent to one another and where the at least two adjacent NFETs have a sourcedrain diffusion region and a leakage path diffusion region under the sourcedrain diffusion region positioned between their respective body regions, wherein the sourcedrain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the sourcedrain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the sourcedrain diffusion but at relatively lower concentrations than the sourcedrain diffusion, thereby presenting a lower barrier to junction leakage than the sourcedrain regions.
8. The pair of adjacent SRAM cells of claim 7, wherein the body regions of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region are coupled to an external bias voltage through the leakage path diffusion region.
9. The pair of adjacent SRAM cells of claim 7, wherein the body regions of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region are coupled to ground through the leakage path diffusion region.
10. The pair of adjacent SRAM cells of claim 7, wherein the body regions of each of the NFETs from the first and second adjacent SRAM cells sharing a leakage path diffusion region further are linked to the body region of another adjacent NFET from their respective SRAM cell with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
11. The pair of adjacent SRAM cells of claim 10 wherein each of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region between body regions are pass gate NFETs, and where the NFETs from the respective SRAM cells having a body region linked to the body region of the pass gate NFETs by leakage path diffusion regions are inverter NFETs.
12. The pair of adjacent SRAM cells of claim 10 wherein each of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region between body regions are inverter NFETs, and where the NFETs from the respective SRAM cells having a body region linked to the body region of the inverter NFETs by leakage path diffusion regions are pass gate NFETs.
13. The pair of adjacent SRAM cells of claim 7, wherein each SRAM cell is a six transistor SRAM cell, and where the body regions of the four NFETs of each of the six transistor CMOS SRAM cells are all linked together with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
14. The SRAM array of claim 7 wherein the NFETs are fabricated in (100) crystal orientation silicon regions.
15. The SRAM array of claim 7 wherein the PFETs are fabricated in (110) crystal orientation silicon regions.
16. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, each of the adjacent SRAM cells comprising:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled inverters; and
where at least one of the PFETs from the first SRAM cell and at least one of the PFETs from the second SRAM cell share a leakage path between body regions, the respective PFETs sharing a leakage path being adjacent to one another and where the at least two adjacent PFETs have a sourcedrain diffusion region and a leakage path diffusion region under the sourcedrain diffusion region positioned between their respective body regions, wherein the sourcedrain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the sourcedrain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the sourcedrain diffusion but at relatively lower concentrations than the sourcedrain diffusion, thereby presenting a lower barrier to junction leakage than the sourcedrain regions.
17. The SRAM array of claim 16 wherein the NFETs are fabricated in (100) crystal orientation silicon regions.
18. The SRAM array of claim 16 wherein the PFETs are fabricated in (110) crystal orientation silicon regions.
19. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, where each of the SRAM cells have two longitudinal and two lateral sides, the adjacent SRAM cells sharing a longitudinal side, each of the adjacent SRAM cells comprising:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, and
wherein one each of the pass gate NFETs and inverter NFETs are positioned along each of the lateral sides of the SRAM cell, whereby the pass gate NFET and inverter NFET positioned on the same lateral side of the SRAM cell comprise a pair and have body regions linked with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions wherein the shallow sourcedrain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the sourcedrain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the sourcedrain diffusion but at relatively lower concentrations than the sourcedrain diffusion, thereby presenting a lower barrier to junction leakage than the sourcedrain regions.
20. The pair of adjacent SRAM cells of claim 19 where the body regions of the pairs of pass gate NFETs and inverter NFETs arrayed along each of the lateral sides of the first SRAM cell are linked to the body regions of the pairs of pass gate NFETs and inverter NFETs in the adjacent second SRAM cell with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
21. The pair of adjacent SRAM cells of claim 19 where in each of the SRAM cells one of the inverter PFETs is positioned along each of the longitudinal sides of the SRAM cell intermediate between the pairs of pass gate NFETs and inverter NFETs positioned along each of the lateral sides of the SRAM cell.
22. The pair of adjacent SRAM cells of claim 21 where the body regions of the PFETs positioned along the shared longitudinal side of the adjacent first and second SRAM cells are linked with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
23. The pair of adjacent SRAM cells of claim 20 wherein on a first lateral side and along the shared longitudinal side of the first SRAM cell the body region of one of the NFET pass gates of the first SRAM cell is linked to the body region of one of the NFET pass gates of the second SRAM cell with the leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
24. The pair of adjacent SRAM cells of claim 20 wherein on a first lateral side and along the shared longitudinal side of the first SRAM cell the body region of one of the inverter NFETS of the first SRAM cell is linked to the body region of one of the inverter NFETs of the second SRAM cell with the leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions.
25. The pair of adjacent SRAM cells of claim 20, wherein the body regions of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region are coupled to an external bias voltage through the leakage path diffusion regions.
26. The pair of adjacent SRAM cells of claim 20, wherein the body regions of the NFETs from the first and second SRAM cells sharing a leakage path diffusion region are coupled to ground through the leakage path diffusion regions.
27. The pair of adjacent SRAM cells of claim 19 wherein the NFETs are fabricated in (100) crystal orientation silicon regions.
28. The pairs of adjacent SRAM cells of claim 19 wherein the PFETs are fabricated in (110) crystal orientation silicon regions.
29. An SRAM array comprising a plurality of SRAM cells organized in rows and columns,
wherein each of the SRAM cells have two longitudinal sides and two lateral sides, the SRAM cells further comprising:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where the at least two adjacent NFETs have a sourcedrain diffusion region and a leakage path diffusion region under the sourcedrain diffusion region positioned between their respective body regions, wherein the sourcedrain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the sourcedrain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the sourcedrain diffusion but at relatively lower concentrations than the sourcedrain diffusion, thereby presenting a lower barrier to junction leakage than the sourcedrain regions, and
where each of the SRAM cells arrayed in a particular row of the SRAM array share longitudinal sides with two other SRAM cells positioned in the same row, except for at least two of the SRAM cells one longitudinal side of each coincides with a termination point of the row, and where the at least two adjacent NFETs of each SRAM cell arrayed in the particular row of the SRAM array having body regions linked by the leakage path diffusion region have their body regions further linked to the body regions of NFETs contained in adjacent SRAM cells sharing longitudinal sides with the SRAM cell with leakage path diffusion regions positioned beneath adjacent shallow sourcedrain diffusion regions, except for the at least two of the SRAM cells having one longitudinal side coinciding with the termination point of the row which have at least one pair of NFETs having a body region linked to the body regions of NFETs positioned in one SRAM cell on a longitudinal side opposite from the termination point of the row with leakage path diffusion regions positioned beneath adjacent shallow sourcedrain diffusion regions; and
whereby a continuous chain of NFETS having body regions linked with leakage path diffusion regions positioned beneath adjacent shallow sourcedrain diffusion regions exists across the particular row of the SRAM array.
30. The SRAM array of claim 29 where a body region of at least one PFET in each SRAM cell arrayed along the particular row of the SRAM array is linked to a body region of a PFET positioned in an adjacent SRAM cell sharing a longitudinal side with a leakage path diffusion region positioned beneath adjacent shallow sourcedrain diffusion regions.
31. The SRAM array of claim 29 wherein the NFETs are fabricated in (100) crystal orientation silicon regions.
32. The SRAM array of claim 29 wherein the PFETs are fabricated in (110) crystal orientation silicon regions.
33. The SRAM array of claim 29 where the at least two NFETs sharing a leakage path diffusion region (between body regions) in at least one of the SRAM cells having a longitudinal side coinciding with one of the termination points of the particular row have their body regions coupled to a bias voltage on the lateral side coinciding with one of the termination points of the particular row.
34. The SRAM array of claim 29 where the at least two NFETs sharing a leakage path diffusion region (between body regions) in at least one of the SRAM cells having a longitudinal side coinciding with one of the termination points of the particular row have their body regions coupled to ground on the lateral side coinciding with one of the termination points of the particular row.
35. A microprocessor fabricated on a CMOS hybrid orientation substrate, wherein the microprocessor comprises a logic portion and a cache memory portion, wherein the cache memory portion further comprises at least one CMOS SRAM array and where:
the logic portion comprises, in part, PFETs fabricated in (110) crystal orientation bulk silicon regions and NFETs fabricated in (100) crystal orientation SOI silicon regions, wherein the NFETs in the logic portion have floating body regions; and
the CMOS SRAM array comprises a plurality of CMOS SRAM cells comprising, in part, PFETs fabricated in (110) crystal orientation silicon regions and NFETs fabricated in (100) crystal orientation SOI silicon regions, wherein at least a portion of the NFETs in the CMOS SRAM cells have body regions linked to body regions of adjacent NFETs with leakage path diffusion regions formed beneath adjacent shallow sourcedrain diffusions wherein the sourcedrain diffusion regions extend fractionally into a surface silicon layer and the leakage path diffusion regions extend from bottoms of the sourcedrain diffusions down to an SOI buried-oxide layer, and where the leakage path diffusion regions are counter-doped with the same dopant type as the sourcedrain diffusions but at relatively lower concentrations than the sourcedrain diffusions, thereby presenting a lower barrier to junction leakage than the sourcedrain regions.
36. A method of forming an SRAM array comprising a plurality of SRAM cells, each of the SRAM cells comprising a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET and the SRAM cell further comprises a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, the method comprising:
forming a buried oxide layer in a silicon wafer, the buried oxide layer positioned between a surface silicon layer and a silicon substrate;
forming a plurality of PFET and NFET gates above body regions in the surface silicon layer;
forming a leakage path diffusion region between at least a pair of adjacent NFET body regions wherein the leakage path diffusion region is counter-doped with a same dopant type as a shallow sourcedrain diffusion to be formed in another step but at relatively lower concentration than the shallow sourcedrain diffusions, thereby presenting a lower barrier to junction leakage than the sourcedrain regions, the leakage path diffusion region extending to the buried oxide layer; and
forming the shallow sourcedrain diffusions above the leakage path diffusion regions, the shallow sourcedrain diffusions extending fractionally into the surface silicon layer
37. The method of claim 36 wherein the silicon wafer comprises (100) crystal orientation silicon, the method further comprising:
prior to the formation of PFETs in the substrate, forming (110) crystal orientation silicon regions; and
forming the PFETs in the (110) crystal orientation silicon regions.
38. The method of claim 36 wherein the leakage path diffusion region is formed between an adjacent inverter NFET and a pass gate NFET of an SRAM cell.
39. The method of claim 36 wherein each SRAM cell is a six transistor SRAM cell, and where a leakage path diffusion region is formed linking the body regions of the four NFETs comprising the SRAM cell.
40. The method of claim 36 wherein the NFETs having body regions linked by formation of a leakage path diffusion region are located in adjacent SRAM cells.
41. The method of claim 36 wherein NFETs across a bit line row traversing a plurality of SRAM cells have body regions linked by formation of a leakage path diffusion region.
42. An SRAM memory comprising:
peripheral logic fabricated in a high-performance silicon substrate;
an SRAM array comprised of a plurality of SRAM cells, wherein the SRAM cells are arrayed in rows and columns and further comprise:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, where
body regions of NFETs arrayed along a column of SRAM cells coinciding with a bit line are linked by leakage path diffusion regions beneath adjacent shallow source drain diffusion regions, thereby forming a chain of linked body regions.
43. The SRAM memory of claim 42 where the high-performance silicon substrate of the peripheral logic comprises a strained silicon region.
44. The SRAM memory of claim 42 where the high-performance silicon substrate of the peripheral logic comprises a hybrid orientation substrate, where the NFETs are fabricated in (100) crystal orientation silicon regions and PFETs are fabricated in (11 O) crystal orientation silicon regions.
45. The SRAM memory of claim 42 where a column of SRAM cells coinciding with a bit line starts at a first SRAM cell and terminates at a last SRAM cell, there being intermediate SRAM cells disposed between the first and last SRAM cells, where the chain of linked body regions of NFETs are coupled to a selective bias voltage at the first SRAM cell and at the last SRAM cell along the column.
46. The SRAM memory of claim 45 where the selective bias voltage is ground.
47. The SRAM memory of claim 45 where the column starting at the first SRAM cell and ending at the last SRAM cell and coinciding with the bit line comprises sixteen SRAM cells.
48. The SRAM memory of claim 45 where a side of each SRAM cell coinciding with the bit line is relatively short when compared to a side of each SRAM cell running orthogonal to the bit line row, whereby the reduced dimension of the side of the SRAM cell coinciding with the bit line row serves to reduce the resistance of a path formed by the leakage path regions joining the body regions of the NFETs along the bit line row.
49. An SRAM memory comprising:
peripheral logic comprised of CMOS NFETs and PFETs, where the NFETs are fabricated in bulk silicon regions and the PFETs are fabricated in SOI silicon regions, where body regions of the PFETs are floating; and
an SRAM array comprised of a plurality of SRAM cells, wherein the SRAM cells are arrayed in rows and columns and further comprise:
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters,
where body regions of NFETs along a column of SRAM cells coinciding with a bit line are linked by leakage path diffusion regions beneath adjacent shallow source drain diffusion regions, thereby forming a chain of linked body regions.
50. The SRAM memory of claim 49 where at least two PFETs from adjacent SRAM cells are linked by leakage path diffusion regions beneath adjacent shallow sourcedrain diffusion regions.
51. The SRAM memory of claim 49 where the PFETs of the peripheral logic are fabricated in (110) crystal orientation SOI silicon regions.
52. The SRAM memory of claim 49 where the PFETs of the SRAM array are fabricated in (110) crystal orientation silicon regions.
53. The SRAM memory of claim 52 where the PFETs of the SRAM array are further fabricated in bulk regions.
54. The SRAM memory of claim 49 where a column of SRAM cells coinciding with a bit line starts at a first SRAM cell and terminates at a last SRAM cell, there being intermediate SRAM cells disposed between the first and last SRAM cells, where the chain of linked body regions of NFETs are coupled to a selective bias voltage at the first SRAM cell and at the last SRAM cell along the column.
55. The SRAM memory of claim 54 where the selective bias voltage is ground.
56. The SRAM memory of claim 54 where the column starting at the first SRAM cell and ending at the last SRAM cell and coinciding with the bit line comprises sixteen SRAM cells.
57. The SRAM memory of claim 54 where a side of each SRAM cell coinciding with the bit line is relatively short when compared to a side of each SRAM cell running orthogonal to the bit line row, whereby the reduced dimension of the side of the SRAM cell coinciding with the bit line row serves to reduce the resistance of a path formed by the leakage path regions joining the body regions of the NFETs along the bit line row.
58. A method of forming an SRAM memory comprised of an SRAM array portion and a peripheral logic portion, where the SRAM array portion is comprised of a plurality of SRAM cells, and where each of the SRAM cells further comprises a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET and the SRAM cell further comprises a pair of NFET pass gates coupling a pair of bit lines to the cross-coupled CMOS inverters, the method comprising:
forming a high-performance silicon substrate portion in a silicon wafer;
forming circuits comprising the peripheral logic portion of the SRAM memory in the high-performance silicon substrate portion of the silicon wafer;
forming the SRAM array portion of the SRAM memory by:
forming a buried oxide layer in the silicon wafer, the buried oxide layer positioned between a surface silicon layer and a silicon substrate;
forming a plurality of PFET and NFET gates above body regions in the surface silicon layer;
forming a leakage path diffusion region between at least a pair of adjacent NFET body regions wherein the leakage path diffusion regions are counter-doped with a same dopant type as a shallow as a shallow sourcedrain diffusion to be formed in another step but at a relatively lower concentration than the shallow sourcedrain diffusions, thereby presenting a lower barrier to junction leakage than the sourcedrain regions, the leakage path diffusion region extending to the buried oxide layer; and
forming the shallow sourcedrain diffusions above the leakage path diffusion regions, the shallow sourcedrain diffusions extending fractionally into the surface silicon layer.
59. The method of claim 58 where the high-performance silicon substrate portion comprises a hybrid orientation substrate having (100) crystal orientation silicon regions and (110) crystal orientation silicon regions.
60. The method of claim 58 where the high-performance silicon substrate portion comprises a strained silicon region.