1. A wireless communication system comprising:
external equipment; and
an apparatus comprising:
a transceiver for transmitting and receiving data packets to and from the external equipment; and
a frequency matched unit for compensating an offset due to latency that may occur during communication between the apparatus and the external equipment by adding a clock value corresponding to predetermined frames to a clock value of a system clock if power save mode is transited to normal mode.
2. The wireless communication system of claim 1, wherein the external equipment further comprises at least one additional apparatus, and wherein at least one of said apparatuses is a master apparatus and at least one of said apparatuses is a slave apparatus.
3. The wireless communication system of claim 2, wherein each master apparatus controls each said slave apparatus associated with the master.
4. The wireless communication system of claim 3, wherein the frequency matching unit of each said associated slave apparatus adds an offset value to each slave clock so as to synchronize said slave clock with the clock of the master apparatus.
5. The wireless communication system of claim 3, wherein the master apparatus manages each said associated slave apparatus in the normal mode and in the power save mode.
6. The wireless communication system of claim 4, wherein the power save mode is a hold mode, a sniff mode or a park mode.
7. The wireless communication system of claim 2, wherein the master apparatus is a communication terminal.
8. The wireless communication system of claim 6, wherein the communication terminal is a computer, a cellular phone or a printer.
9. A wireless communication apparatus comprising:
a transceiver for transmitting and receiving data packets to and from external equipment; and
a frequency matched unit for compensating an offset due to latency that may occur during communication between the apparatus and the external equipment by adding a clock value corresponding to predetermined frames to a clock value of a system clock if power save mode is transited to normal mode.
10. The wireless communication apparatus of claim 9, wherein the power save mode is a hold mode, a sniff mode or a park mode.
11. The wireless communication apparatus of claim 9, wherein the apparatus is digital equipment.
12. The wireless communication apparatus of claim 9, wherein the apparatus is a cellular phone, a laptop computer, a printer, a personal digital assistant(PDA), a desk top computer, a facsimile, a keyboard, or a joy stick.
13. A wireless communication method comprising:
transmitting and receiving data packets to and from external equipment; and
compensating an offset due to latency that may occur during communication between an apparatus and the external equipment by adding a clock value corresponding to predetermined frames to a clock value of a system clock if power save mode is transited to normal mode.
14. The wireless communication method of claim 13, wherein the power save mode is a hold mode, a sniff mode or a park mode.
15. A method of operating a wireless communication system, comprising:
selecting an apparatus to serve as a master apparatus, wherein any additionally connected apparatus is a slave apparatus, and all connected apparatuses make up a piconet;
calculating a frequency hopping row and a channel access code of a channel within the piconet based on a system clock of the master apparatus; wherein each said slave apparatus adds an offset value to each slave clock to synchronize the slave clock with the system clock of the master apparatus;
transmitting and receiving data packets to and from the apparatuses in the piconet; and
compensating an offset due to latency that may occur during communication between the apparatuses in the piconet by adding a clock value corresponding to predetermined frames to a clock value of a system clock if power save mode is transited to normal mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
Having thus described our invention, what we claim as new and desire to secure by Letters Patent is:
1. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
providing a first p-type single crystalline silicon region with a concentration level greater than 11019 atomscm3 on a first substrate,
forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a third silicon region over said second carbon-doped epitaxial region, doping said third silicon region n-type,
forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 11019 atoMcm3,
forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said fifth silicon epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second carbon-doped region, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon,
forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth compressively strained Si1-w-qGewCq epitaxial region.
2. A method according to claim 1 further comprising the steps of
forming a gate dielectric region over said fourth region of compressively strained Si1-sGes region, and
forming a conducting region over said gate dielectric region.
3. The method according to claim 2 further including the steps of:
forming a blanket dielectric layer over and above an entire vertical column structure,
forming a first conducting via through said blanket dielectric layer in contact to said first p-type silicon region,
forming a second conducting via through said blanket dielectric layer in contact to said fifth silicon epitaxial region at the top of said vertical structure, and
forming a third conducting via through said blanket dielectric layer in contact to said conducting region.
4. A method according to claim 1 wherein said first, third and fifth silicon regions, second carbon-doped region, fourth compressively strained Si1-w-qGewCq epitaxial region and sixth compressively strained Si1-sGes region are formed by a process selected from the group consisting of UHV-CVD, RTCVD, LPCVD, APCVD and MBE.
5. A method according to claim 1 wherein said first silicon region is doped p-type by a process selected from the group consisting of ion implantation followed by annealing or in situ doping.
6. A method according to claim 1 wherein said silicon epitaxial region is relaxed with respect to the upper surface of said fourth compressively strained Si1-w-qGewCq region.
7. A method according to claim 1 wherein said fifth silicon epitaxial region may be single crystal silicon or poly silicon or poly SiGe.
8. A method according to claim 1 wherein said vertical structure is formed by a process selected from the group consisting of reactive ion etching and ion beam milling.
9. A method according to claim 1 wherein said sidewall of said vertical structure is in the crystalline plane (100), and perpendicular to the substrate plane.
10. A method according to claim 1 wherein said strained sixth compressively strained Si1-sGes region on said sidewall of said vertical structure is strained with respect to said first p-type silicon region.
11. A method according to claim 2 wherein said gate dielectric region is selected from the group consisting of an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combination.
12. A method according to claim 2 wherein said conducting region is selected from the group consisting of metal, metal silicide, doped poly silicon, and doped poly SiGe.
13. A method according to claim 1 wherein said second carbon-doped epitaxial region is doped p-type in the range from 11019 to 11021 atomscm3.
14. A method according to claim 1 wherein said fifth silicon epitaxial region is doped p-type to a level in range from 11019 to 11021 atomscm3.
15. A method according to claim 1 wherein said sixth compressively strained Si1-sGes region is autodoped p-type in the region adjacent to said first p-type silicon region, second carbon-doped epitaxial region, fourth compressively strained Si1-w-qGewCq region and fifth silicon epitaxial region while autodoped n-type in the region adjacent to said n-type third silicon region after annealing.
16. A method according to claim 1 wherein the autodoping in the sixth compressively strained Si1-sGes region and the activation of the dopants in the doped regions are achieved by a process selected from the group consisting of rapid thermal annealing, furnace annealing and laser annealing.
17. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
providing a first p-type single crystalline silicon region with a concentration level greater than 11019 atomscm3 on a first substrate,
forming a second carbon-doped epitaxial region over said first p-type silicon region, doping said second carbon-doped epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a third silicon epitaxial region over said second carbon-doped epitaxial region, doping said third silicon region n-type,
forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon region, doping said fourth compressively strained Si1-w-qGewCq region p-type to a concentration level greater than 11019 atomscm3,
forming a fifth silicon epitaxial region over said fourth compressively strained Si1-w-qGewCq region, doping said silicon epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a vertical structure comprising at least one sidewall extending from said first p-type silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region, and fifth region of silicon,
forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second carbon-doped region, over said third region of silicon to said fourth region of Si1-w-qGewCq epitaxial region, and
forming a seventh silicon region over said sixth compressively strained Si1-sGes region.
18. A method according to claim 17 further comprising the steps of
forming a gate dielectric region over said seventh silicon region,
forming a conducting region over said gate dielectric region.
19. The method according to claim 18 further including the steps of:
forming a blanket dielectric layer over and above an entire vertical column structure,
forming a first conducting via through said blanket dielectric layer in contact to said first p-type silicon region,
forming a second conducting via through said blanket dielectric layer in contact to said fifth silicon epitaxial region at the top of said vertical structure, and
forming a third conducting via through said blanket dielectric layer in contact to said conducting region.
20. A method according to claim 17 wherein said first, third and fifth silicon regions, second carbon-doped region, fourth compressively strained Si1-w-qGewCq epitaxial region and sixth compressively strained Si1-sGes region are formed by a process selected from the group consisting of UHV-CVD, RTCVD, LPCVD, APCVD and MBE.
21. A method according to claim 17 wherein said first silicon region is doped p-type by a process selected from the group consisting of ion implantation followed by annealing and in situ doping.
22. A method according to claim 17 wherein said silicon epitaxial region is relaxed with respect to the upper surface of said fourth compressively strained Si1-w-qGewCq region.
23. A method according to claim 17 wherein said fifth silicon epitaxial region may be single crystal silicon or poly silicon or poly SiGe.
24. A method according to claim 17 wherein said vertical structure is formed by a process selected from the group consisting of reactive ion etching and ion beam milling.
25. A method according to claim 17 wherein said sidewall of said vertical structure is in the crystalline plane (100), and perpendicular to the substrate plane.
26. A method according to claim 17 wherein said strained sixth compressively strained Si1-sGes region on said sidewall of said vertical structure is strained with respect to said first p-type silicon region.
27. A method according to claim 18 wherein said gate dielectric layer is selected from the group consisting of an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combination.
28. A method according to claim 18 wherein said conducting region is selected from the group consisting of metal, metal silicide, doped poly silicon, and doped poly SiGe.
29. A method according to claim 17 wherein said second carbon-doped epitaxial region is doped p-type in the range from 11019 to 11021 atomscm3.
30. A method according to claim 17 wherein said fifth silicon epitaxial region is doped p-type to a level in range from 11019 to 11021 atomscm3.
31. A method according to claim 17 wherein said sixth compressively strained Si1-sGes region and seventh silicon region are autodoped p-type in the region adjacent to said first p-type silicon region, second carbon-doped epitaxial region, fourth compressively strained Si1-w-qGewCq region and fifth silicon epitaxial region while autodoped n-type in the region adjacent to said n-type third silicon region after annealing.
32. A method according to claim 17 wherein the autodoping in the sixth compressively strained Si1-sGes region and seventh silicon region and the activation of the dopants in the doped regions are achieved by a process selected from the group consisting of rapid thermal annealing, furnace annealing and laser annealing.
33. A method of preparing a vertical channel of a field effect transistor comprising the steps of:
providing a first p-type single crystalline silicon region with a concentration level greater than 11019 atomscm3 on a first substrate,
forming a second compressively strained Si1-x-yGexCy epitaxial region over said first silicon region, doping said second Si1-x-yGexCy region p-type to a concentration level greater than 11019 atomscm3,
forming a third silicon epitaxial region over said second region, doping said third region n-type,
forming a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon epitaxial region, doping said fourth Si1-w-qGewCq epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a fifth silicon epitaxial region over said fourth Si1-w-qGewCq epitaxial region, doping said fifth silicon region p-type to a concentration level greater than 11019 atomscm3,
forming a vertical structure comprising at least one sidewall extending from said first silicon region, second region, third silicon epitaxial region, fourth Si1-w-qGewCq epitaxial region, and fifth region,
forming a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region, over said third region of silicon to said fourth Si1-w-qGewCq epitaxial region.
34. A method according to claim 33 further comprising the steps of
forming a gate dielectric region over said sixth compressively strained Si1-sGes region,
forming a conducting region over said gate dielectric region.
35. The method according to claim 34 further including the steps of:
forming a blanket dielectric layer over and above an entire vertical column structure,
forming a first conducting via through said blanket dielectric layer in contact to said first p-type silicon region,
forming a second conducting via through said blanket dielectric layer in contact to said fifth silicon epitaxial region at the top of said vertical structure, and
forming a third conducting via through said blanket dielectric layer in contact to said conducting region.
36. A method according to claim 33 wherein said first, third and fifth silicon regions second carbon-doped region, fourth compressively strained Si1-w-qGewCq epitaxial region and sixth compressively strained Si1-sGes region are formed by a process selected from the group consisting of UHV-CVD, RTCVD, LPCVD, APCVD and MBE.
37. A method according to claim 33 wherein said third silicon region is doped n-type by a process selected from the group consisting of ion implantation followed by annealing and in situ doping.
38. A method according to claim 33 wherein said third silicon region is relaxed with respect to the upper surface of said second Si1-x-yGexCy region.
39. A method according to claim 33 wherein said fifth silicon region is relaxed with respect to the upper surface of said fourth Si1-w-qGewCq epitaxial region.
40. A method according to claim 33 wherein said fifth silicon region may be single crystal silicon or poly silicon or poly SiGe.
41. A method according to claim 33 wherein said vertical structure is formed by a process selected from the group consisting of reactive ion etching and ion beam milling.
42. A method according to claim 33 wherein said sidewall of said vertical structure is substantially in the crystalline plane (110), and perpendicular to the substrate plane.
43. A method according to claim 33 wherein said sixth strained Si1-sGes region on said sidewall of said vertical structure is strained with respect to said first silicon region.
44. A method according to claim 33 wherein said gate dielectric layer is selected from the group consisting of an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combination.
45. A method according to claim 33 wherein said conducting region is selected from the group consisting of metal, metal silicide, doped poly silicon, and doped poly SiGe.
46. A method according to claim 33 wherein said second region is doped p-type in the range from 11019 to 11021 atomscm3.
47. A method according to claim 33 wherein said fifth silicon epitaxial region is doped p-type to a level in range from 11019 to 11021 atomscm3.
48. A method according to claim 33 wherein said sixth strained Si1-sGes region is autodoped p-type in the region adjacent to said first p-type region, second region, fourth region and fifth region while autodoped n-type in the region adjacent to said third n-type silicon region after annealing.
49. A method according to claim 33 wherein the autodoping in said sixth strained Si1-sGes region and the activation of the dopants in the doped regions are achieved by a process selected from the group consisting of rapid thermal annealing, furnace annealing and laser annealing.
50. A method of preparing an inverter made of the vertical field effect CMOS transistors comprising the steps of:
forming a first silicon epitaxial region on a first single crystalline substrate, doping said first silicon epitaxial region n-type to a concentration level greater than 11019 atomscm3,
forming a second Si1-i-jGeiCj epitaxial region over said first n-type silicon region,
forming a third silicon epitaxial region over said second Si1-i-jGeiCj region, doping said third silicon epitaxial region p-type,
forming a fourth strained Si1-yCy epitaxial region over said third p-type silicon region, doping said fourth strained Si1-yCy region n-type to a concentration level greater than 11019 atomscm3,
forming a fifth silicon region over said fourth n-type strained Si1-yCy region, doping said fifth silicon region n-type to a concentration level greater than 11019 atomscm3,
forming a first vertical column structure comprising at least one sidewall extending from said first silicon region, over said second strained Si1-xCx region, over said third region of p-type silicon, over said fourth region of strained Si1-yCy, to said fifth silicon region,
forming a sixth silicon region over a region of said at least one sidewall of said first vertical structure,
forming a first gate dielectric region over said sixth silicon region,
forming a first gate conducting region over said first gate dielectric region,
masking and etching a nearby region to expose said first single crystalline substrate,
forming a seventh p-type silicon region with a concentration level greater than 11019 atomscm3 on said first single crystalline substrate,
forming an eighth carbon-doped epitaxial region over said seventh region, doping said eighth region p-type to a concentration level greater than 11019 atomscm3,
forming a ninth silicon epitaxial region over said eighth region, doping said ninth region n-type,
forming a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth region, doping said tenth Si1-w-qGewCq region p-type to a concentration level greater than 11019 atomscm3,
forming an eleventh silicon epitaxial region over said tenth Si1-w-qGewCq region, doping said eleventh silicon region p-type to a concentration level greater than 11019 atomscm3,
forming a second vertical column structure comprising said seventh silicon region, eighth carbon-doped region, ninth silicon region, tenth Si1-w-qGewCq region, and eleventh silicon epitaxial region,
forming a twelvth strained Si1-sGes region over the outer perimeter of the second vertical column structure,
forming a second gate dielectric region over the outer perimeter of said twelfth region,
forming a second gate conducting region over the outer perimeter of said second gate dielectric region.
51. The method according to claim 50 further comprising the steps of:
forming a first blanket dielectric layer over and above the first entire vertical column structure,
forming a first conducting region through the above first blanket dielectric layer in contact to said first n-type silicon region,
forming a second conducting region through the above first blanket dielectric layer in contact to said fifth silicon region at the top of the above said first vertical column structure,
forming a third conducting region through the above first blanket dielectric layer in contact to the conducting region on the outer perimeter of said first vertical column structure,
forming a second blanket dielectric layer over and above the second entire vertical column structure,
forming a fourth conducting region through the above second blanket dielectric layer in contact to said seventh p-type silicon region,
forming a fifth conducting region through the above second blanket dielectric layer in contact to said eleventh p-type silicon region at the top of the second vertical column structure,
forming a sixth conducting region through the above second blanket dielectric region in contact to said second gate conducting region on the outer perimeter of said second vertical column structure, and
forming a third dielectric region on said first substrate in between said first and second vertical column structures to serve as device isolation.
52. A method according to claim 51 wherein said fourth conducting region is coupled to said first conducting region, said sixth conducting region is coupled to said third conducting region and said fifth conducting region is coupled to said second conducting region via conducting material.
53. A method according to claim 50 wherein the sidewall of said first vertical column is in the plane (100), and perpendicular to the substrate plane.
54. A method according to claim 50 wherein the sidewall of said second vertical column is in the plane (110), and perpendicular to the substrate plane.
55. A method according to claim 50 wherein said twelfth strained SiGe region is a silicon layer.
56. A method of preparing an inverter made of the vertical field effect CMOS transistors comprising the steps of:
forming a first relaxed Si1-iGei epitaxial region on a first single crystalline substrate, doping said first Si1-iGei epitaxial region n-type to a concentration level greater than 11019 atomscm3,
forming a second carbon-doped SiGe epitaxial region over said first n-type Si1-iGei region, doping said second SiGe epitaxial region n-type to a concentration level greater than 11019 atomscm3,
forming a third relaxed Si1-iGei epitaxial region over said second carbon-doped SiGe region, doping said third silicon epitaxial region p-type,
forming a fourth tensile strained silicon epitaxial region over said third p-type Si1-iGei region, doping said fourth strained silicon region n-type to a concentration level greater than 11019 atomscm3,
forming a fifth relaxed Si1-iGei region over said fourth n-type strained silicon region, doping said Si1-iGei region n-type to a concentration level greater than 11019 atomscm3,
forming a first vertical column structure comprising at least one sidewall extending from said first relaxed Si1-iGei region, over said second carbon-doped SiGe region, over said third region of p-type relaxed Si1-iGei, over said fourth strained silicon region to said fifth SiGe region,
forming a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure,
forming a first gate dielectric region over said sixth silicon region,
forming a first gate conducting region over said first gate dielectric region,
masking and etching a nearby region to expose said first single crystalline substrate,
forming a seventh p-type silicon region with a concentration level greater than 11019 atomscm3 on said first single crystalline substrate,
forming an eighth carbon-doped epitaxial region over said seventh region, doping said eighth region p-type to a concentration level greater than 11019 atomscm3,
forming a ninth silicon epitaxial region over said eighth region, doping said ninth epitaxial region n-type,
forming a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth epitaxial region, doping said tenth Si1-w-qGewCq region p-type to a concentration level greater than 11019 atomscm3,
forming an eleventh silicon epitaxial region over said tenth Si1-w-qGewCq region, doping said eleventh silicon epitaxial region p-type to a concentration level greater than 11019 atomscm3,
forming a second vertical column structure comprising said seventh silicon region, eighth carbon-doped region, ninth silicon epitaxial region, tenth Si1-w-qGewCq region, and eleventh silicon epitaxial region,
forming a twelfth strained Si1-sGes region over the outer perimeter of the above second vertical column structure,
forming second gate a dielectric region over the outer perimeter of the above twelfth region, and
forming a second gate conducting region over the outer perimeter of said second gate dielectric region,
57. The method according to claim 56 further comprising the steps of:
forming a first blanket dielectric layer over above said first entire vertical column structure,
forming a first conducting region through the above first blanket dielectric layer in contact to said first n-type silicon region,
forming a second conducting region through the above said first blanket dielectric layer in contact to said fifth silicon region at the top of the above said first vertical column structure,
forming a third conducting region through the above said first blanket dielectric layer in contact to the conducting region on the outer perimeter of said first vertical column structure,
forming a second blanket dielectric layer over and above said second entire vertical column structure,
forming a fourth conducting region through the above second blanket dielectric layer in contact to said seventh p-type silicon region,
forming a fifth conducting region through the above second blanket dielectric layer in contact to said eleventh p-type silicon region at the top of said second vertical column structure,
forming a sixth conducting region through the above second blanket dielectric region in contact to said second gate conducting on the outer perimeter of said second vertical column structure, and
forming a third dielectric region on said first substrate in between said first and second vertical column structures to serve as device isolation.
58. A method according to claim 56 wherein said fourth conducting region is coupled to said first conducting region, said sixth conducting region is coupled to said third conducting region and said fifth conducting region is coupled to said second conducting region via conducting material.
59. A method according to claim 56 wherein the sidewall of said first vertical column is in the plane (100), and perpendicular to the substrate plane.
60. A method according to claim 56 wherein the sidewall of said second vertical column is in the plane (110), and perpendicular to the substrate plane.
61. A field effect transistor comprising:
a substrate,
a first single crystalline silicon region having a p-type concentration level greater than 11019 atomscm3 on said substrate,
a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 11019 atomscm3,
a third silicon epitaxial region over said second carbon-doped region doped n-type,
a fourth compressively strained Si1-w-qGewCq epitaxial region over said third silicon epitaxial region, said Si1-w-qGewCq region having a p-type concentration level greater than 11019 atomcm3,
a fifth silicon containing region over said fourth Si1-w-qGewCq region having a p-type concentration level greater than 11019 atomscm3,
a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Si1-w-qGewCq epitaxial region to said fifth region of silicon,
a sixth compressively strained Si1-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Si1-w-qGewCq epitaxial region,
a gate dielectric region over said sixth compressively strained Si1-sGes region, and
a gate conducting region over said dielectric region.
62. The field effect transistor according to claim 61 further including:
a blanket dielectric layer over and above said vertical structure,
a first conducting via through said blanket dielectric layer in contact to said first p-type silicon region,
a second conducting via through said blanket dielectric layer in contact to said fifth p-type silicon containing region at the top of said vertical structure, and
a third conducting via through said blanket dielectric layer in contact to said gate conducting region.
63. The field effect transistor according to claim 61 wherein said fifth silicon containing region is relaxed with respect to the upper surface of said fourth Si1-w-qGewCq region.
64. The field effect transistor according to claim 61 wherein said fifth silicon containing region is selected from the group consisting of single crystal silicon, poly silicon and poly SiGe.
65. The field effect transistor according to claim 61 wherein said sidewall of said vertical structure is in the crystalline plane (110), and perpendicular to a major surface of said substrate.
66. The field effect transistor according to claim 61 wherein said sixth strained Si1-sGes region on said sidewall of said vertical structure is compressively strained with respect to said first silicon region.
67. The field effect transistor according to claim 61 wherein said gate dielectric region is selected from the group consisting of an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combination thereof.
68. The field effect transistor according to claim 61 wherein said gate conducting region is selected from the group consisting of metal, metal silicide, doped poly silicon and doped poly SiGe.
69. The field effect transistor according to claim 61 wherein said second carbon-doped region is doped p-type in the range from 11019 to 11021 atomscm3.
70. The field effect transistor according to claim 61 wherein said fifth silicon containing region is doped p-type in the range from 11019 to 11021 atomscm3.
71. The field effect transistor according to claim 61 wherein said sixth strained Si1-sGes region is doped p-type in the region adjacent to said first p-type region, second region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.
72. The field effect transistor according to claim 61 further including a seventh silicon region over said sixth compressively strained Si1-sGes region and below said gate dielectric region.
73. The field effect transistor according to claim 72 wherein said sixth strained Si1-sGes region and said seventh silicon region are doped p-type in the region adjacent to said first p-type region, second region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.
74. The field effect transistor according to claim 61 further including an eighth compressively strained Si1-x-yGexCy epitaxial region over said first silicon region, said eighth compressively strained Si1-x-yGexCy epitaxial region having a p-type concentration level greater than 11019 atomcm3 .
75. The field effect transistor according to claim 74 wherein said third silicon region is relaxed with respect to the upper surface of said eighth Si1-x-yGexCy region.
76. A method according to claim 74 wherein said sixth strained Si1-sGes region is doped p-type in the region adjacent to said first p-type region, eighth epitaxial region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.
77. An inverter comprising:
a first silicon epitaxial region on a first single crystalline substrate having a n-type concentration level greater than 11019 atomscm3,
a second Si1-i-jGeiCj epitaxial region over said first n-type silicon region,
a third silicon epitaxial region over said second Si1-i-jGeiCj epitaxial region doped p-type,
a fourth strained Si1-yCy epitaxial region over said third p-type silicon region having a n-type concentration level greater than 11019 atomscm3,
a fifth region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said fourth n-type strained Si1-yCy region having a n-type concentration level greater than 11019 atomscm3,
a first vertical structure comprising at least one sidewall extending from said first silicon region, over said second region of strained Si1-xCx region, over said third region of p-type silicon, over said fourth region of strained Si1-yCy to said fifth region,
a sixth silicon region over a region of said at least one sidewall of said vertical structure,
a first gate dielectric region over said sixth silicon region, and
a first gate conducting region over said gate dielectric region,
a seventh p-type silicon epitaxial region on said first single crystalline substrate having a concentration level greater than 11019 atomscm3,
an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 11019 atomscm3,
a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type,
a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 11019 atomcm3,
an eleventh region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said tenth Si1-w-qGewCq region having a p-type concentration level greater than 11019 atomscm3,
a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si1-w-qGewCq epitaxial region, to said eleventh silicon epitaxial region,
a twelfth strained Si1-sGes region over a region of said at least one sidewall of said vertical structure,
a second gate dielectric region over said twelfth strained Si1-sGes region, and
a second gate conducting region over said gate dielectric region.
78. The field effect transistor according to claim 77 further comprising:
a first blanket dielectric layer over and above said first vertical structure,
a first conducting via through said first blanket dielectric layer in contact to said first n-type silicon region,
a second conducting via through said first blanket dielectric layer in contact to said fifth region at the top of said first vertical structure,
a third conducting via through said first blanket dielectric layer in contact to said first gate conducting region,
a second blanket dielectric layer over and above said second vertical structure,
a fourth conducting via through said second blanket dielectric layer in contact to said seventh p-type silicon epitaxial region,
a fifth conducting via through said second blanket dielectric layer in contact to said eleventh p-type silicon containing region at the top of the above vertical structure,
a sixth conducting via through said second blanket dielectric layer in contact to said second gate conducting region, and
a third dielectric region on said first substrate in between said first and second vertical structures to provide device isolation.
79. The inverter according to claim 78 wherein said fourth conducting via is coupled to said first conducting via, said sixth conducting via is coupled to said third conducting via and said fifth conducting via is coupled to said second conducting via by way of conducting material.
80. The inverter according to claim 77 wherein said sidewall of said first vertical structure is in the plane (100), and perpendicular to a major surface of said substrate.
81. The inverter according to claim 77 wherein said sidewall of said second vertical structure is in the plane (110), and perpendicular to a major surface of said substrate.
82. The inverter according to claim 77 wherein said twelfth strained SiGe region is a silicon region.
83. An inverter comprising:
a first relaxed Si1-iGei epitaxial region on a first single crystalline substrate, said first Si1-iGei epitaxial layer doped n-type to a concentration level greater than 11019 atomscm3,
a second tensile strained silicon epitaxial region over said first p-type Si1-iGei region, said second silicon epitaxial region doped n-type to a concentration level greater than 11019 atomscm3,
a third relaxed Si1-iGei epitaxial region over said second silicon region, said third silicon epitaxial region doped p-type,
a fourth tensile strained silicon epitaxial region over said third p-type Si1-iGei region, said fourth strained silicon region doped n-type to a concentration level greater than 11019 atomscm3,
a fifth region selected from a group consisting of relaxed Si1-iGei, poly silicon and poly SiGe over said fourth n-type strained silicon region, said fifth Si1-iGei region doped n-type to a concentration level greater than 11019 atomscm3,
a first vertical structure comprising at least one sidewall extending from said first relaxed SiGe region, over said second strained silicon epitaxial region, over said third p-type relaxed Si1-iGei epitaxial region, over said fourth strained silicon epitaxial region to said fifth region,
a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure,
a first gate dielectric region over said sixth silicon region, and
a first gate conducting region over said gate dielectric region,
a seventh p-type silicon epitaxial region on a first single crystalline substrate having a concentration level greater than 11019 atomscm3,
an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 11019 atomscm3,
a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type,
a tenth compressively strained Si1-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 11019 atomscm3,
an eleventh region selected from a group consisting of single crystalline silicon, poly Si and poly SiGe over said tenth Si1-w-qGewCq region having a p-type concentration level greater than 11019 atomscm3,
a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon epitaxial region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si1-w-qGewCq epitaxial region, to said eleventh silicon epitaxial region,
a twelfth strained Si1-sGes region over a region of said at least one sidewall of said second vertical structure,
a second gate dielectric region over said twelfth silicon region, and
a second gate conducting region over said gate dielectric region.
84. The field effect transistor according to claim 83 further comprising:
a first blanket dielectric layer over and above said first vertical structure,
a first conducting via through said first blanket dielectric layer in contact to said sixth silicon region in the area on top of said first n-type silicon layer,
a second conducting via through said first blanket dielectric layer in contact to said fifth silicon containing region at the top of said first vertical structure,
a third conducting via through said first blanket dielectric layer in contact to said first gate conducting layer,
a second blanket dielectric layer over and above said vertical structure,
a fourth conducting via through said second blanket dielectric layer in contact to said seventh p-type silicon region,
a fifth conducting via through said second blanket dielectric layer in contact to said twelfth silicon region in the area over said eleventh p-type silicon epitaxial region at the top of the above said first vertical structure,
a sixth conducting via through said second blanket dielectric layer in contact to said second gate conducting region, and
a third dielectric region on said first substrate in between said first and second vertical structures to provide device isolation.
85. The inverter according to claim 84 wherein said fourth conducting via is coupled to said first conducting via, said sixth conducting via is coupled to said third conducting via and said fifth conducting via is coupled to said second conducting via conducting material.
86. The inverter according to claim 83 wherein said sidewall of said first vertical structure is in the plane (100), and perpendicular to a major surface of said substrate.
87. The inverter according to claim 83 wherein said sidewall of said second vertical structure is in the plane (110), and perpendicular to a major surface of said substrate.
88. The inverter according to claim 83 wherein said twelfth strained SiGe region is a silicon region.