1. An apparatus for ion storage and analysis comprising:
at least two or more rows of parallel placed electrode array wherein each electrode array includes at least two or more parallel bar-shaped electrodes;
applying different phase of alternating current voltages on different bar electrodes to create alternating electric fields inside the space between two parallel electrodes of different rows of electrode arrays; and
multiple linear ion trapping fields paralleled constructed in the space between the different rows of electrode arrays which are open to adjacent each other without a real barrier.
2. The apparatus of claim 1 wherein further introducing low pressure collision gases to lower the kinetic energy of the captured ions so that they can condense to parallel series of narrow ion cloud strips around the axes series paralleled to the bar electrodes.
3. The apparatus of claim 1 wherein the upper electrodes array plane and the lower electrodes array plane is planar paralleled and edge aligned up and down as well as boundary electrodes are set around the volume enclosed by two adjacent rows of parallel electrodes array.
4. The apparatus of claim 3 wherein the sizes of the bar electrodes on one electrodes array are the same as well as the potentials of the boundary electrodes in the electrodes array placed on the side of electrodes array paralleled to the bar electrodes are the median of potentials of adjacent bar electrodes.
5. The apparatus of claim 4 wherein the potentials of bar electrodes in the parallel electrodes array are set according to the sequence: +V, \u2212V, +V, \u2212V . . . the alternating voltage V contains at least one high frequency voltage component and the potentials of boundary electrodes paralleled to the bar electrodes mention above are set to zero.
6. The apparatus of claim 5 wherein the voltage V makes of pure high frequency voltage component.
7. The apparatus of claim 5 wherein the voltage V contains a high frequency voltage component and a low frequency voltage component below 1000 Hz.
8. The apparatus of claim 1 wherein further contain groups of electric switches for creating high or low frequency voltages by switching on and off rapidly.
9. The apparatus of claim 1 wherein through holes or outlet slits or outlet net are placed on at least part of the boundary electrodes for ion extracting out of the ITA.
10. The apparatus of claim 1 wherein outlet slits or outlet net are placed on at least one part of the bar electrodes in parallel electrode array for ion extracting out of the IT.
11. The apparatus of claim 1 wherein including voltage generators and the coupling equipments for creating dipole fields between two adjacent rows of parallel electrodes array for ion extracting out of the ITA.
12. The apparatus of claim 1 wherein the shapes of the bar electrodes are planar, all main surface of bar electrodes are paralleled to each other.
13. The apparatus of claim 1 wherein one or more rows of electrode arrays can be made of Printed Circuit Board (PCB).
14. The apparatus of claim 13 wherein the PCBs for planar electrodes array construction contains the multilayer PCBs with at least one surface layer for planar electrodes array shaped pattern.
15. The apparatus of claim 13 wherein the manufacture of electrode array boards including multilayer PCB with electric components mounting and pads for down-leads on at least parts of the electric conductive layers.
16. The apparatus of claim 13 wherein the two rows of electrodes arrays can be made of two PCBs separately, and fixed together by several boundary electrode boards.
17. The apparatus of claim 1 wherein further includes an ion detector in order to detect ions ejected out. The detector should be located at the end of one of the ion trapping axis and outside the ITA.
18. (canceled)
19. (canceled)
20. A method for ion storage and analysis comprising:
Parallel electrode arrays consisted of bar electrodes paralleled to each other.
Alternating current (AC) voltages with different phases are assigned to the bar electrodes to create alternating electric fields between the pair of bar electrodes.
Furthermore, multiple conjoint linear ion trapping fields were paralleled constructed in the space between the different rows of electrode arrays. The ions can be trapped inside these fields and cooled down, then be separated and analyzed by their mass to charge ratio differences.
21-37. (canceled)
38. A method of ion storage and analysis, uses at least 2 or more rows of parallel places electrode array wherein each electrode array includes at least two or more parallel bar-shaped electrodes; applying difference phases of alternating current voltages on different bar electrodes to create alternating electric fields inside the space between two parallel electrodes of different rows of electrode arrays, creating multiple linear ion trapping fields. The ions are then separated within these trapping fields due to their differences in nature.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory device comprising:
a memory; and
a memory control circuit for controlling said memory, wherein:
said memory control circuit includes:
a bank busy circuit for variably setting a bank busy time that controls different bank cycle times;
a read data input circuit for inputting read data output from said memory in variable input timing;
a write data output circuit for outputting write data to said memory in variable output timing;
a command control circuit for issuing a command to said memory based on a memory command output from said bank busy circuit, thereby controlling different command interfaces;
a write mask circuit for controlling different write masks;
an initial sequence control circuit for controlling memories different in the initial sequence; and
an address generation circuit for controlling different address interfaces, and
said memory control circuit controls different memories using the same hardware.
2. The semiconductor memory device according to claim 1, wherein:
said bank busy circuit includes:
a program register for variably setting the bank busy time; and
a bank busy counter for setting a value set on said program register, and then counting down the set value for each clock cycle when a bank n is accessed for turning on, and
said bank busy circuit provides said command control circuit with a memory command indicating cleared bank busy when the logic value of said bank busy counter becomes zero, thereby controlling memories different in the bank cycle time.
3. The semiconductor memory device according to claim 1, wherein:
said read data input circuit includes a first program register for variably setting the input timing of the read data output from said memory for controlling memories different in the access time, and inputs the read data output from said memory based on a set value on the first program register in variable input timing, and
said write data output circuit comprises a second program register for variably setting the output timing of the write data output to said memory, and adjusts the write data output timing based on a set vale on the second program register.
4. The semiconductor memory device according to claim 1, wherein said bank busy circuit switches the bank busy time using a switch.
5. The semiconductor memory device according to claim 1, wherein:
said write mask circuit relates to mask control for the write data output to said memory, and has a program register for switching between masking write operation using a Variable Write function when an FCRAM or an NWRAM is used, and masking the write operation using a Data Mask function when a DDR-SDRAM is used.
6. The semiconductor memory device according to claim 1, wherein:
said write mask circuit relates to mask control for the write data output to said memory, and has a switch for switching between masking of write operation using a Variable Write function when an FCRAM or an NWRAM is used, and masking of the write operation using a Data Mask function when a DDR-SDRAM is used.
7. The semiconductor memory device according to claim 1, wherein:
said address generation circuit relates to address generation of memories different in address assignment, and includes a program register for switching address generation logic.
8. The semiconductor memory device according to claim 1, wherein:
said address generation circuit relates to address generation of memories different in address assignment, and includes a switch for switching address generation logic.
9. The semiconductor memory device according to claim 1, wherein:
said initial sequence control circuit relates to control of memories different in the initial sequence, includes a program register for variably changing the issue sequence of commands including mode register set, extension mode register set, auto refresh, and all bank pre-charge, and for variably changing set values on a mode register and an extension mode register, controls said memories different in the initial sequence using the same circuit, and issues an initial sequence command including the mode register set, the extension mode register set, the auto refresh, and the all bank pre-charge to said command control circuit.
10. The semiconductor memory device according to claim 1, wherein:
said initial sequence control circuit relates to control of memories having different initial sequences, includes a switch for variably changing the issue sequence of commands including mode register set, extension mode register set, auto refresh, and all bank pre-charge, and for variably changing set values on a mode register and an extension mode register, controls said memories different in the initial sequence using the same circuit, and issues an initial sequence command including the mode register set, the extension mode register set, the auto refresh, and the all bank pre-charge to said command control circuit.
11. The semiconductor memory device according to claim 1, comprising a power supply capable of adjusting a power supply output level supplied for said memory.
12. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 1 on a board, wherein:
said memory is different in the package size or the pin assignment, only the board for mounting the memory is changed, and one type of mother board is used for connecting the board for mounting the memory thereon when the memory different in the package size or the pin assignment is mounted.
13. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 2 on a board, wherein:
said memory is different in the package size or the pin assignment, only the board for mounting the memory is changed, and one type of mother board is used for connecting the board for mounting the memory thereon when the memory different in the package size or the pin assignment is mounted.
14. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 3 on a board, wherein:
said memory is different in the package size or the pin assignment, only the board for mounting the memory is changed, and one type of mother board is used for connecting the board for mounting the memory thereon when the memory different in the package size or the pin assignment is mounted.
15. The mount-type semiconductor device according to claim 12, wherein the board for mounting the memory thereon is a DIMM (Dual Inline Memory Module).
16. The mount-type semiconductor device according to claim 13, wherein the board for mounting the memory thereon is a DIMM (Dual Inline Memory Module).
17. The mount-type semiconductor device according to claim 14, wherein the board for mounting the memory thereon is a DIMM (Dual Inline Memory Module).
18. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 1 on a board, wherein:
said memory is different in whether a terminating resistor is incorporated or not, and when the memory which is different in whether a terminating resistor is incorporated or not is mounted, a terminating resistor is not mounted on a DIMM (Dual Inline Memory Module) for the memory incorporating a terminating resistor, and a terminating resistor is attached to a DIMM for the memory not incorporating a terminating resistor, and one type of mother board is provided for connecting to the board for mounting the memory thereon.
19. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 2 on a board, wherein:
said memory is different in whether a terminating resistor is incorporated or not, and when the memory which is different in whether a terminating resistor is incorporated or not is mounted, a terminating resistor is not mounted on a DIMM (Dual Inline Memory Module) for the memory incorporating a terminating resistor, and a terminating resistor is attached to a DIMM for the memory not incorporating a terminating resistor, and one type of mother board is provided for connecting to the board for mounting the memory thereon.
20. A mount-type semiconductor device for mounting said semiconductor memory device according to claim 3 on a board, wherein:
said memory is different in whether a terminating resistor is incorporated or not, and when the memory which is different in whether a terminating resistor is incorporated or not is mounted, a terminating resistor is not mounted on a DIMM (Dual Inline Memory Module) for the memory incorporating a terminating resistor, and a terminating resistor is attached to a DIMM for the memory not incorporating a terminating resistor, and one type of mother board is provided for connecting to the board for mounting the memory thereon.