We claim:
1. A trench isolation method comprising:
forming a trench in a semiconductor substrate using a mask pattern defining an active area;
sequentially stacking an oxide layer and a nitride pad layer on the sidewall of the trench and forming an insulation layer in the trench;
removing the mask pattern down to the upper surface of the semiconductor substrate of the active area; and
forming a capping layer of an insulating material, the capping layer filling a recess at the upper edge of the trench, the recess generated by etching the nitride pad layer formed on the sidewalls of the trench during removing the mask pattern.
2. The trench isolation method of claim 1, wherein the mask pattern is formed of a nitride layer.
3. The trench isolation method of claim 1, wherein the oxide layer is a thermal oxide layer formed by a thermal process.
4. The trench isolation method of claim 3, wherein the thickness of the thermal oxide layer is formed to be 50-250 .
5. The trench isolation method of claim 1, wherein the pad nitride layer is formed by low pressure chemical vapor deposition (LPCVD).
6. The trench isolation method of claim 5, wherein the thickness of the pad nitride layer is formed to be 50-250 .
7. The trench isolation method of claim 1, wherein forming an insulation layer comprises:
filling the inside of the trench with an insulating material; and
planarizing the resultant structure in which the insulating material is formed using the mask pattern defining the active area as a planarizing stopper.
8. The trench isolation method of claim 1, wherein the removing of the mask pattern is performed by wet-etching.
9. The trench isolation method of claim 1, wherein the capping layer is formed by forming an insulating material by self epitaxial growth (SEG), and then removing the insulating material layer down to the upper surface of the semiconductor substrate of the active area so that only the insulating material layer filled in the recess is exposed.
10. The trench isolation method of claim 1, further comprising forming a second oxide layer, wherein the second oxide layer is formed on the nitride pad layer before the insulation layer is formed in the trench.
11. The trench isolation method of claim 1, wherein forming a capping layer of an insulating material comprises:
forming an insulating material layer for burying the recess in the entire surface of the resultant substrate; and
forming a capping layer filling the recess by removing the insulating material layer down to the upper portion of the isolation layer and the upper surface of the semiconductor substrate so that only the insulating material layer filling the recess is exposed.
12. The trench isolation method of claim 11, wherein the insulating material layer burying the recess is formed by chemical vapor deposition (CVD).
13. The trench isolation method of claim 12, wherein the insulating material layer comprises a material selected from a group consisting of an oxide, a nitride, and an oxynitride.
14. The trench isolation method of claim 11, wherein the forming of a capping layer filling the recess is performed by dry-etching.
15. A trench isolation method comprising:
forming a trench in a semiconductor substrate using a mask pattern defining an active area;
sequentially stacking a first oxide layer, a nitride pad layer and a second oxide layer on the sidewall of the trench and forming an isolation layer in the trench;
removing the mask pattern to expose the upper surface of the semiconductor substrate of the active area; and
forming a capping layer of an insulating material, the capping layer filling a recess at the upper edge of the trench recess generated by etching the nitride pad layer formed on the sidewalls of the trench during removal of the mask pattern.
16. The trench isolation method of claim 15, wherein the mask pattern is formed of a nitride.
17. The trench isolation method of claim 15, wherein the first oxide layer is a thermal oxide layer formed by a thermal process.
18. The trench isolation method of claim 17, wherein the thickness of the first thermal oxide layer is formed to be 50-250 .
19. The trench isolation method of claim 15, wherein the pad nitride layer is formed by LPCVD.
20. The trench isolation method of claim 19, wherein the thickness of the pad nitride layer is formed to be 50-250 .
21. The trench isolation method of claim 15, wherein the second oxide layer is a thermal oxide layer formed by a thermal process.
22. The trench isolation method of claim 21, wherein the thickness of the second thermal oxide layer is formed to be 50-250 .
23. The trench isolation method of claim 15, wherein the forming of an isolation layer in the trench comprises:
filling the inside of the trench with an insulating material; and
planarizing the resultant structure in which the insulating material is formed using the mask pattern defining the active area as a planarizing stopper.
24. The trench isolation method of claim 15, wherein the removing of the mask pattern is performed by wet-etching.
25. The trench isolation method of claim 15, wherein the capping layer is formed by forming an insulating material layer by self epitaxial growth (SEG), and then removing the insulating material layer down to the upper surface of the semiconductor substrate of the active area so that only the insulating material layer filled in the recess is exposed.
26. The trench isolation method of claim 15, wherein forming a capping layer of an insulating material comprises:
forming an insulating material layer for burying the recess on the entire surface of the resultant substrate; and
forming a capping layer filling the recess by removing the insulating material layer down to the upper portion of the isolation layer and the upper surface of the semiconductor substrate so that only the insulating material layer filling the recess is exposed.
27. The trench isolation method of claim 26, wherein the insulating material layer burying the recess is formed by CVD.
28. The trench isolation method of claim 27, wherein the insulating material layer comprises a material selected from a group consisting of an oxide, a nitride, and an oxynitride.
29. The trench isolation method of claim 26, wherein the forming of a capping layer filling the recess is performed by dry-etching.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A thin film transistor (TFT), comprising:
a semiconductor layer including:
a source region and a drain region;
a channel region between the source region and the drain region; and
a lightly doped drain (LDD) region between the channel region and the source region or between the channel region and the drain region;
a gate insulation layer on the source region, the drain region, the channel region, and the LDD region; and
a gate electrode on the gate insulation layer,
wherein the gate insulation layer has a first thickness at portions on the source region, the drain region, and the LDD region and a second thickness at a portion on which the gate electrode is arranged, the second thickness being greater than the first thickness, and a projected range of ions doped in the semiconductor layer extends to a first depth from a surface of the semiconductor layer in the LDD region, and
wherein the difference between the second thickness and the first thickness equals the first depth.
2. The TFT of claim 1, wherein the first depth satisfies the following mathematical expression:
(thickness of the semiconductor layer2)\u2212100 \u212b\u2266first depth\u2266(thickness of the semiconductor layer2)+100 \u212b.\u2003\u2003<Mathematical Expression 1>
3. The TFT of claim 1, wherein the semiconductor layer is crystallized using an excimer laser annealing or sequential lateral solidification method.