1. A method for fabricating a strained-silicon CMOS transistor, comprising:
providing a semiconductor substrate having a first active region for fabricating a first transistor, a second active region for fabricating a second transistor, and an isolation structure disposed between the first active region and the second active region;
forming a sourcedrain region for the first transistor and a sourcedrain region for the second transistor;
forming a first etching stop layer, a first stress layer, and a second etching stop layer on the first transistor, the second transistor, and the isolation structure;
forming a first patterned photoresist on the second etching stop layer of the first active region;
performing a first etching process to remove the second etching stop layer and a portion of the first stress layer of the second active region;
removing the first patterned photoresist; and
performing a second etching process by utilizing the second etching stop layer of the first active region as a mask to remove the remaining first stress layer of the second active region.
2. The method for fabricating a strained-silicon CMOS transistor of claim 1, wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.
3. The method for fabricating a strained-silicon CMOS transistor of claim 1, wherein the first stress layer is a high tensile stress film.
4. The method for fabricating a strained-silicon CMOS transistor of claim 1 further comprising utilizing methyl fluoride (CH3F) for controlling the magnitude of the second etching process.
5. The method for fabricating a strained-silicon CMOS transistor of claim 1 further comprising:
depositing a metal layer on the first transistor and the second transistor;
performing a rapid thermal anneal process to form a salicide layer on the first transistor and the second transistor; and
removing the un-reacted metal layer.
6. The method for fabricating a strained-silicon CMOS transistor of claim 5 further comprising:
forming a second stress layer on the second etching stop layer of the first active region and the first etching stop layer of the second transistor of the second active region after performing the second etching process;
forming a third etching stop layer on the second stress layer;
forming a second patterned photoresist on the third etching stop layer of the second active region;
performing a third etching process to remove the third etching stop layer and a portion of the second stress layer of the first active region;
removing the second patterned photoresist; and
performing a fourth etching process by utilizing the third etching stop layer of the second active region as a mask to remove the remaining second stress layer of the first active region and the second stress layer between the first active region and the second active region, such that the second stress layer and the first stress layer comprises a gap therebetween.
7. The method for fabricating a strained-silicon CMOS transistor of claim 6 further comprising utilizing methyl fluoride (CH3F) for controlling the magnitude of the second etching process.
8. The method for fabricating a strained-silicon CMOS transistor of claim 6, wherein the second stress layer is a high compressive stress film.
9. The method for fabricating a strained-silicon CMOS transistor of claim 6 further comprising removing a portion of the first etching stop layer of the second active region, such that the remaining first etching stop layer comprises a depth of 20 angstroms.
10. The method for fabricating a strained-silicon CMOS transistor of claim 6 further comprising:
depositing a dielectric layer on the second etching stop layer and the third etching stop layer after performing the fourth etching process; and
performing an etching process to remove a portion of the dielectric layer, the second etching stop layer, the third etching stop layer, the first stress layer, the second stress layer, and the first etching stop layer to form a plurality of contact holes.
11. The method for fabricating a strained-silicon CMOS transistor of claim 5 further comprising:
forming a second stress layer on the second etching stop layer of the first active region and the first etching stop layer of the second transistor of the second active region after performing the second etching process; and
performing a third etching process to remove the second stress layer of the first active region and the second stress layer disposed between the first active region and the second active region, such that the second stress layer and the first stress layer comprises a gap therebetween.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of performing an X2 interface setup in a wireless communication system, the method comprising:
transmitting, by a first home evolved NodeB (HeNB), an X2 setup request message to a second HeNB via an HeNB gateway (GW), the X2 setup request message including a first cell access mode indicator indicating a cell access mode of the first HeNB;
receiving, by the first HeNB, an X2 setup response message from the second HeNB via the HeNB GW, the X2 setup response message including a second cell access mode indicator indicating a cell access mode of the second HeNB;
determining, by the first HeNB, whether an X2 interface between the first HeNB and the second HeNB is available or not for an X2 handover based on the cell access mode of the second HeNB; and
transmitting, by the first HeNB, an X2 handover request message to the second HeNB when the X2 interface is available,
wherein the first HeNB and the second HeNB operate with one of an open mode, a hybrid mod, and a closed mode, the open mode indicating that an HeNB provides services to any user equipments (UEs), the hybrid mode indicating that a closed subscriber group (CSG) cell provides services to its associated CSG member UEs and to non-CSG member UEs, the closed mode indicating that a CSG cell provides services only to its associated CSG member UEs, and
wherein each of the first HeNB and the second HeNB has a different closed subscriber group (CSG) identifier (ID).
2. The method of claim 1, wherein the X2 interface is available for the X2 handover when the second cell access mode indicator indicates that the cell access mode of the second HeNB is the open mode or the hybrid mode.
3. The method of claim 2, wherein the X2 interface is available for the X2 handover when the second cell access mode indicator indicates that the cell access mode of the second HeNB is the closed mode and a UE is a member of the second HeNB, the UE intending to handover to the second HeNB.
4. A method of performing access control by a home evolved NodeB (HeNB) gateway (GW) in a wireless communication system, the method comprising:
receiving a cell access mode of a target HeNB and membership information of a user equipment (UE);
receiving stored closed subscriber group (CSG) subscription information for the UE from a mobility management entity (MME);
determining whether an X2 interface between a source eNB and the target HeNB is available or not for an X2 handover based on the cell access mode of the target HeNB, the membership information, and the stored CSG subscription information for the UE; and
performing UE access control via the X2 interface when the X2 interface is available for the X2 handover,
wherein the membership information is determined based on a CSG identifier (ID) received from the target eNB and the UE’s CSG whitelist.
5. The method of claim 4, wherein the X2 interface is available for the X2 handover when the cell access mode of the target HeNB is a open mode or a hybrid mode.
6. The method of claim 4, wherein a direct X2 interface is available for the X2 handover when the cell access mode of the target HeNB is a closed mode and the UE is a member of the target HeNB, the UE intending to handover to the target HeNB.