1. A method of forming a semiconductor resistor structure comprising the steps of:
a) providing an interlevel dielectric material structure;
b) etching a trough structure in said dielectric structure;
c) depositing a layer of conductive material having lateral and vertical portions in said trough structure;
d) depositing a layer of insulator material having lateral and vertical portions above said layer of conductive material in said trough structure;
e) alternating deposition of conductive and insulator material layers according to steps c) and d) to form said resistor structure having properties tailored according to types and thicknesses of said conductive and insulator materials;
f) planarizing a surface of said resistor structure; and,
g) forming a via structure above said planarized surface to connect a top surface of each said vertical portions of said conductive film layers of said resistor structure to an adjacent wire level.
2. The method according to claim 1, wherein the alternating conductive layers comprise a refractory metal having a high sheet resistance.
3. The method according to claim 2, wherein the alternating insulator film layers provide vertical seif-ballasting, and the metal film layers exhibit a lateral self-ballasting effect created by the high resistance of the refractory metal.
4. The method according to claim 1, wherein the step of alternating deposition of conductive and insulator material layers according to steps c) and d) enables tuning of a Temperature Coefficient of Resistance value for said resistor structure.
5. The method according to claim 1, wherein the step of alternating deposition of conductive and insulator material layers according to steps c) and d) form a resistor structure having increased ESD robustness.
6. A method of forming a semiconductor resistor structure comprising the steps of:
a) providing an interlevel dielectric material structure;
b) depositing a layer of conductive material in a planar orientation;
c) depositing a layer of insulator material having in a planar orientation above said layer of conductive material;
d) alternating deposition of conductive and insulator material layers according to steps b) and c) to form a multi-stack resistor structure having properties tailored according to types and thicknesses of said conductive and insulator materials; and,
e) forming one or more vertically oriented via structures to connect each of said conductive film layers of said resistor structure to an adjacent wire level, at least two of the conductive material layers being electrically connected in parallel.
7. The method according to claim 6, wherein the alternating conductive layers comprise a refractory metal having a high sheet resistance.
8. The method according to claim 7, wherein the alternating insulator film layers provide vertical seif-ballasting, and the metal film layers exhibit a lateral self-ballasting effect created by the high resistance of the refractory metal.
9. The method according to claim 6, wherein the step of alternating deposition of conductive and insulator material layers according to step d) enables tuning of a Temperature Coefficient of Resistance value for said resistor structure.
10. The method according to claim 6, wherein the step of alternating deposition of conductive and insulator material layers according to steps c) and d) form a resistor structure having increased ESD robustness.
11. The method according to claim 6, wherein said step e) of forming one or more via structures to connect or more of said conductive films include utilizing single or dual damascene processes for forming said vias to connect one or more conductive films in parallel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flat display device comprising:
a plurality of pixels arranged in matrix on a substrate;
a plurality of scanning lines provided for respective rows of the pixels, which select a group of pixels in each of the rows;
a scanning line driving circuit to which the scanning lines are connected; and
a scanning switching circuit which determines whether input original image data is a still image or a moving image and switches an operation of the scanning line driving circuit to one of interlaced scanning and noninterlaced scanning in accordance with a determination result.
2. The flat display device according to claim 1, wherein the scanning switching circuit switches the operation of the scanning line driving circuit to the noninterlaced scanning when the original image data is determined as a moving image, and switches the operation of the scanning line driving circuit to the interlaced scanning when the original image data is determined as a still image.
3. The flat display device according to claim 1, wherein the scanning switching circuit is externally supplied with a reference value to determine whether the original image data is a moving image or a still image.
4. The flat display device according to claim 3, wherein the reference value varies with a power consumption mode.
5. The flat display device according to claim 1, wherein the scanning switching circuit calculates a difference between the original image data and one-frame-old image data, and determines that the original image data is a moving image when a sum of differences for one frame is larger than a given value and that the original image data is a still image when the sum is not larger than the given value.
6. The flat display device according to claim 1, wherein the scanning switching circuit calculates a difference between the original image data corresponding to a determination range and one-frame-old image data corresponding to the determination range, and determines that the original image data is a moving image when a sum of differences for the determination range is larger than a given value and that the original image data is a still image when the sum is not larger than the given value.
7. The flat display device according to claim 3, wherein the scanning switching circuit calculates a difference between the original image data and one-frame-old image data, and determines that the original image data is a moving image when a sum of differences for one frame is larger than the reference value and that the original image data is a still image when the sum is not larger than the reference value.
8. The flat display device according to claim 1, further comprising:
a plurality of signal lines provided for respective columns of the pixels, which supply an image signal to a group of pixels in each of the columns; and
a signal line driving circuit to which the signal lines are connected,
wherein the scanning switching circuit includes a display image control unit which determines whether the original image data is a moving image or a still image, and a switching unit which switches the operation of the scanning line driving circuit to one of the interlaced scanning and the noninterlaced scanning, and
the display image control unit includes a data conversion circuit which selects image data corresponding to a scanning line to be driven from the original image data, and supplies the switching unit with the selected image data and a sync signal thereof.
9. The flat display device according to claim 8, further comprising:
a display panel having the substrate; and
an information processing unit electrically connected to the display panel through a signal supply wire,
wherein the switching unit is provided in the display panel, and the display image control unit is provided in the information processing unit.
10. The flat display device according to claim 8, further comprising:
a display panel having the substrate; and
an information processing unit electrically connected to the display panel through a signal supply wire,
wherein the display image control unit and the switching unit are provided in the display panel.
11. The flat display device according to claim 1, wherein when the scanning line driving circuit performs the interlaced scanning, the scanning switching circuit scans the scanning lines at intervals of l lines in an order designated as {k+(j+1)}-th line, {k+2(j+1)}-th line, . . . in an n-th field, and scans the scanning lines at intervals of j lines in an order designated as (k+1)-th line, {k+1+(j+1)}-th line, {k+1+2(j+1)}-th line, . . . in an (n+1)-th field, to thereby form one screen.
12. The flat display device according to claim 1, wherein the switching unit switches between the interlaced scanning and the noninterlaced scanning within a same field.
13. The flat display device according to claim 1, wherein the switching unit switches between the interlaced scanning and the noninterlaced scanning during one of a vertical blanking interval and a horizontal blanking interval.
14. A method of driving a flat display device including a plurality of pixels arranged in matrix on a substrate, a plurality of signal lines provided for respective columns of the pixels, which supply an image signal to a group of pixels in each of the columns, a plurality of scanning lines provided for respective rows of the pixels, which select a group of pixels in each of the rows, a signal line driving circuit to which the signal lines are connected, a scanning line driving circuit to which the scanning lines are connected, and a scanning switching circuit to which original image data is input,
the method comprising:
determining whether the original image data is a still image or a moving image in the scanning switching circuit; and
switching an operation of the scanning line driving circuit to one of interlaced scanning and noninterlaced scanning in accordance with a determination result.
15. The method according to claim 14, wherein the scanning switching circuit switches the operation of the scanning line driving circuit to the interlaced scanning when the original image data is determined as a still image, and switches-the operation of the scanning line driving circuit to the noninterlaced scanning when the original image data is determined as a moving image.
16. The method according to claim 14, wherein the scanning switching circuit calculates a difference between the original image data and one-frame-old image data, and determines that the original image data is a moving image when a sum of differences for one frame exceeds a given value and that the original image data is a still image when the sum is not larger than the given value.
17. The method according to claim 14, wherein the scanning switching circuit calculates a difference between the original image data corresponding to a determination range and one-frame-old image data corresponding to the determination range, and determines that the original image data is a moving image when a sum of differences for the determination range exceeds a given value and that the original image data is a still image when the sum is not larger than the given value.
18. The method according to claim 14, wherein the scanning switching circuit is supplied with a reference value to determine whether the original image data is a moving image or a still image, the switching circuit calculates a difference between the original image data and one-frame-old image, compares a sum of differences for one frame with an external input reference value, and determines that the original image data is a moving image when the sum exceeds the reference value and that the original image data is a still image when the sum is not larger than the reference value.
19. The method according to claim 14, wherein the scanning switching circuit includes a display image control unit which determines whether the original image data is a moving image or a still image, and a switching unit which switches the operation of the scanning line driving circuit to one of the interlaced scanning and the noninterlaced scanning, and the display image control unit selects image data corresponding to a scanning line to be driven by the scanning line driving circuit from the original image data, and supplies the switching unit with the selected image data and a sync signal corresponding to the image data.
20. The method according to claim 14, wherein when the scanning line driving circuit performs the interlaced scanning, the scanning switching circuit scans the scanning lines at intervals of j lines in an order designated as {k+(j+1)}-th line, {k+2(j+1)}-th line, . . . in an n-th field, and scans the scanning lines at intervals of l lines in an order designated as (k+1)-th line, {k+1+(j+1)}-th line, {k+1+2(j+1)}-th line, . . . in an (n+1)-th field, to thereby form one screen.