1. A method for programming a group of at least one flash memory cell of an array, comprising:
A. performing a first pass of program verify and programming steps until each flash memory cell of the group attains a threshold voltage that is at least X % of a program verify level but less than the program verify level after the first pass is completed; and
B. performing, after the first pass is completed, a second pass of program verify and programming steps until each flash memory cell of the group attains substantially the program verify level,
wherein (100%\u2013X %) of the program verify level is at least a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to the program verify level.
2. The method of claim 1, wherein the step A comprises a loop of the following steps:
determining whether a flash memory cell of the group has not attained substantially X % of the program verify level, during the program verify step; and
generating a programming pulse for the flash memory cell of the group that has not attained substantially X % of the program verify level, during the programming step.
3. The method of claim 1, wherein the step B comprises a loop of the following steps:
determining whether a flash memory cell of the group has not attained substantially the program verify level, during the program verify step; and
generating a programming pulse for the flash memory cell of the group that has not attained the program verify level, during the programming step.
4. The method of claim 1, wherein the group includes a plurality of flash memory cells to be programmed to multi-level threshold voltages, the method further comprising:
performing the first pass of program verify and programming steps until each flash memory cell of a first sub-group of the group attains a threshold voltage that is at least Y % of a first program verify level but less than the first program verify level, and until each flash memory cell of a second sub-group of the group attains a threshold voltage that is at least Z % of a second program verify level but less than the second program verify level; and
performing the second pass of program verify and programming steps until each flash memory cell of the first sub-group attains substantially the first program verify level, and until each flash memory cell of the second sub-group attains substantially the second program verify level,
wherein (100%\u2013Y %) of the first program verify level and (100%\u2013Z %) of the second program verify level are each at least a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to a higher of the first and second program verify levels.
5. The method of claim 4, wherein (100%\u2013Y %) of the first program verify level and (100%\u2013Z %) of the second program verify level are each a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to a higher of the first and second program verify levels.
6. The method of claim 1, wherein (100%\u2013X %) of the program verify level is a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to the program verify level.
7. The method of claim 1, wherein the at least one flash memory cell of the group is contained within a page of the array.
8. The method of claim 7, wherein the page of the array is situated between VSS (source bias voltage) lines and between drain bit line junctions.
9. The method of claim 1, further comprising:
storing a respective address of each flash memory cell of the group in a page buffer.
10. A system for programming a group of at least one flash memory cell of an array, comprising:
means for performing a first pass of program verify and programming steps until each flash memory cell of the group attains a threshold voltage that is at least X % of a program verify level but less than the program verify level after the first pass is completed; and
means for performing, after the first pass is completed, a second pass of program verify and programming steps until each flash memory cell of the group attains substantially the program verify level,
wherein (100%\u2013X %) of the program verify level is at least a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to the program verify level.
11. The system of claim 10, wherein the means for performing the first pass comprises:
means for determining whether a flash memory cell of the group has not attained substantially X % of the program verify level, during the program verify step; and
means for generating a programming pulse for the flash memory cell of the group that has not attained substantially X % of the program verify level, during the programming step.
12. The system of claim 10, wherein the means for performing the second pass comprises:
means for determining whether a flash memory cell of the group has not attained substantially the program verify level, during the program verify step; and
means for generating a programming pulse for the flash memory cell of the group that has not attained the program verify level, during the programming step.
13. The system of claim 10, wherein the group includes a plurality of flash memory cells to be programmed to multi-level threshold voltages, the system further comprising:
means for performing the first pass of program verify and programming steps until each flash memory cell of a first sub-group of the group attains a threshold voltage that is at least Y % of a first program verify level but less than the first program verify level, and until each flash memory cell of a second sub-group of the group attains a threshold voltage that is at least Z % of a second program verify level but less than the second program verify level; and
means for performing the second pass of program verify and programming steps until each flash memory cell of the first sub-group attains substantially the first program verify level, and until each flash memory cell of the second sub-group attains substantially the second program verify level,
wherein (100%\u2013Y %) of the first program verify level and (100%\u2013Z %) of the second program verify level are each at least a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to a higher of the first and second program verify levels.
14. The system of claim 13, wherein (100%\u2013Y %) of the first program verify level and (100%\u2013Z %) of the second program verify level are each a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to a higher of the first and second program verify levels.
15. The system of claim 10, wherein (100%\u2013X %) of the program verify level is a maximum potential change to a threshold voltage of a flash memory cell from programming any adjacent flash memory cells to the program verify level.
16. The system of claim 10, wherein the at least one flash memory cell of the group is contained within a page of the array.
17. The system of claim 16, wherein the page of the array is situated between VSS (source bias voltage) lines and between drain bit line junctions.
18. The system of claim 10, further comprising:
a page buffer for storing a respective address of each flash memory cell of the group.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A terminal connecting apparatus for connecting a flat circuit body and a terminal, which terminal includes claws bent perpendicularly at both sides of a bottom wall thereof, comprising:
a receiving base for setting the flat circuit body on a surface thereof;
a pair of guide walls for placing and positioning the terminal between said pair of guide walls so as to arrange front ends of the claws of the terminal opposing toward the flat circuit body;
a pressing member provided slidably between the pair of guide walls to move and approach the receiving base for making the claws penetrate through a conductor of the flat circuit body by pressing the terminal;
an actuator for moving the pair of guide walls close-toapart-from the receiving base so as to position the terminal between the pair of guide walls by making the pair of guide walls close to the receiving base; and
a pair of projections projecting from at least one of surfaces opposing to each other of the pair of guide walls,
wherein each projection slides on an outer surface of one of the claws to scratch and thereby remove a part of the outer surface of the claw and form scratch marks, from a base side thereof, adjacent the bottom wall of the terminal, toward an opposite front end thereof, arranged to penetrate the conductor of the flat circuit body, when the pair of guide walls approaches the receiving base.
2. The terminal connecting apparatus according to claim 1, further comprising an adjusting mechanism capable of changing a projecting length of said projections.