1. A semiconductor memory device comprising:
memory;
a serial data link interface configured to receive serial input data at a serial data input port, and to transfer serial data to a serial data output port;
a control input for receiving an output enable signal that is used to enable the memory device to transfer the serial data to the serial data output port; and
control circuitry responsive to the output enable signal that controls data transfer on the serial data output port.
2. The semiconductor memory device of claim 1 further comprising a second control input for receiving an input enable signal that is used to enable the memory device to receive the serial input data.
3. The semiconductor memory device of claim 2 further comprising a first control output for outputting a second output enable signal and a second control output for outputting a second input enable signal.
4. The semiconductor memory device of claim 1 further comprising a clock input for receiving a clock signal.
5. The semiconductor memory device of claim 1 wherein the memory comprises a plurality of memory banks.
6. The semiconductor memory device of claim 1 further comprising a control output for outputting a second output enable signal.
7. The semiconductor memory device of claim 6, wherein the second output enable signal is the first output signal delayed.
8. The semiconductor memory device of claim 6, wherein the second output enable signal is derived from the first output signal.
9. The semiconductor memory device of claim 1, wherein the serial data link interface is further configured to convert serial input data into parallel data and to transfer the data to the memory.
10. The semiconductor memory device of claim 1, wherein the serial data link interface is further configured to transfer data from the memory into serial output data.
11. The semiconductor memory device of claim 10, wherein the serial data link interface is further configured to convert serial input data into parallel data and parallel data into serial output data.
12. The semiconductor memory device of claim 1, wherein the control circuitry is configured to receive instructions at the serial data input port to control the transfer of serial output data from the memory.
13. The semiconductor memory device of claim 12 further comprising a unique device identification number.
14. The semiconductor memory device of claim 13, wherein the control circuitry controls access to the memory in response to target device address corresponding to the unique device identification number associated with the device, the target device address being contained in a target device address field of the serial input data.
15. The semiconductor memory device of claim 12, wherein the control circuitry controls the transfer of the data from a location in the memory identified in an address field of the serial input data.
16. The semiconductor memory device of claim 1, wherein the memory, the serial data link interface and the control circuitry are located within a single package having a one-side pad architecture.
17. The semiconductor memory device of claim 1, wherein the memory comprises a non-volatile memory bank
18. The semiconductor memory device of claim 17, wherein the non-volatile memory bank is a flash memory bank.
19. The semiconductor memory device of claim 18, wherein the non-volatile memory bank is a NAND flash memory bank.
20. The semiconductor memory device of claim 1 wherein control circuitry is further responsive to a clock signal to control data transfer on the serial data output port.
21. The semiconductor memory device of claim 1 wherein the control circuitry is further configured to require an output enable signal to remain active until the data transfer on the serial output port is completed.
22. A semiconductor memory device comprising:
memory;
a serial data link interface configured to receive serial input data at a serial data input port, and to transfer serial data to a serial data output port;
a first control input for receiving an output enable signal that is used to enable the memory device to transfer the serial data to the serial data output port;
a second control input for receiving an input enable signal that is used to enable the memory device to receive the serial input data;
a clock input for receiving a clock signal; and
control circuitry responsive to the output enable signal that controls data transfer on the serial data output port and to the input enable signal that enables the device to receive the serial input data.
23. The semiconductor memory device of claim 22 wherein the first control input, the second control input, the serial data input port, and the serial data output port are configured to be synchronized with the clock signal.
24. The semiconductor memory device of claim 23 wherein the first control input, the second control input, the serial data input port, and the serial data output port are configured to be synchronized at a double data rate with the rising and falling edges of clock signal.
25. The semiconductor memory device of claim 22 wherein the control circuitry is further responsive to the clock signal to enable the device to receive the serial input data.
26. The semiconductor memory device of claim 22 wherein the control circuitry is configured to require an input enable signal to remain active until a target device address and a command instruction is received.
27. The semiconductor memory device of claim 26 wherein the control circuitry is further configured to require an input enable signal to remain active until a row address is received.
28. The semiconductor memory device of claim 26 wherein the control circuitry is further configured to require an input enable signal to remain active until a column address is received.
29. The semiconductor memory device of claim 26 wherein the control circuitry is further configured to require an input enable signal to remain active until a row address instruction, a column address, and data is received.
30. A method of controlling data transfer from a serial link interface in a semiconductor memory device, the method comprising:
receiving an output enable signal at a control input;
enabling the output of serial output data based on the output enable signal; and
sending a serial output data stream from the serial data link interface.
31. The method of claim 30 wherein the method further comprises:
transferring parallel data between the memory and the serial data link interface; and
converting the parallel data into serial output data prior to sending the serial output data stream from the serial data link interface.
32. The method of claim 30 wherein the semiconductor memory device is a flash memory device.
33. The method of claim 30 wherein the flash memory device is a NAND device.
34. A flash memory system having a plurality of serially connected flash memory devices comprising:
a first flash memory device having a serial data input port, a serial data output port, and a control input port, the first flash memory device configured to receive serial input data and an output enable signal from an external source device, and to send serial output data based on the output enable signal; and
a second flash memory device having a serial data input port, the second flash memory device configured to receive serial input data from the first flash memory device.
35. The flash memory system of claim 34 wherein:
the first flash memory device further includes a control output port, and is configured to send a second output enable signal; and
the second flash memory device further includes a serial data output port and a control input port, and is configured to receive the second output enable signal from the control output port of the first device.
36. The flash memory system of claim 35 wherein the second output enable signal is the first input signal delayed.
37. The flash memory system of claim 35 wherein the second output enable signal is derived from the first output enable signal.
38. The flash memory system of claim 35 wherein the second flash memory device further includes a control output port and is further configured to send serial output data and a third output enable signal to an external target device.
39. The flash memory system of claim 34 wherein the external source device is a controller.
40. The flash memory system of claim 34 wherein the external source device is a flash memory device.
41. The flash memory system of claim 34, wherein:
the first flash memory device further includes a second control input port and a second control output port, and is configured to receive an input enable signal from an external source device, and to send a second input enable signal; and
the second flash memory device further includes a second control input port, and is configured to receive the second input enable signal from the data first flash memory device.
42. The flash memory system of claim 34, wherein a single clock signal is communicated in a cascading signal to each flash memory device of the plurality of serially connected flash memory devices.
43. The flash memory system of claim 34 wherein each of the plurality of flash memory devices further include:
a flash memory bank
a serial data link interface configured to receive serial input data at an serial data input port and transfer the serial input data to the memory bank, and to transfer serial output data to a serial data output port; and
control circuitry that controls data transfer between the serial data link interface and the flash memory bank, and between the serial data link interface and the serial data output port.
44. The flash memory system of claim 43 wherein the flash memory bank is a NAND flash memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for coordinating a computation upon a plurality of data containers deployed at a plurality of nodes, comprising:
at each of the nodes, executing a corresponding process configured for starting a program to perform the computation in response to a command received from a database system; and
at the database system, receiving a statement specifying an external routine for performing the computation and, in response to receiving the statement:
concurrently transmitting a plurality of commands for performing the computation to each said corresponding process;
receiving results from each said process; and
completing processing of the statement based on the results received from each said process.
2. A method for coordinating a computation upon a plurality of data containers deployed at a plurality of nodes, comprising:
receiving a statement at a database system specifying an external routine for performing the computation; and
in response to receiving the statement:
transmitting a plurality of commands for performing the computation to a plurality of respective processes configured for starting a plurality of respective programs to perform the computation in response to the commands;
receiving results from each said process; and
completing processing of the statement based on the results received from each said process.
3. A method according to claim 2, further comprising:
determining a cohort of nodes from among the plurality of nodes capable of performing the computation,
wherein the plurality of the respective processes correspond to the cohort of the nodes.
4. A method according to claim 3, wherein the plurality of nodes includes at least one node not included in the cohort of the nodes.
5. A method according to claim 3, wherein said determining is based on a degree of parallelism supported by each of the nodes.
6. A method according to claim 3, further comprising accessing a registry specifying an association between the programs and the data containers,
wherein said determining is based on the association between the programs and the data containers.
7. A method according to claim 3, further comprising accessing a registry specifying respective attributes for the data containers,
wherein said determining is based on matching the respective attributes for the data containers with a parameter in the statement.
8. A method according to claim 3, further comprising accessing a registry specifying a partitioning function associated with the programs and the data containers,
wherein said determining is based on the results from executing the partitioning function associated with the programs and the data containers.
9. A method according to claim 2, wherein at least some of the programs execute in parallel.
10. A computer-readable medium bearing instructions for coordinating the computation, said instructions being arranged, upon execution by one or more processors to perform the method according to claim 1.