1. A malfunction predicting unit comprising:
a level reduction unit configured to reduce an input digital signal by a preset level to generate a level-reduced signal;
a first buffer gate unit configured to generate a first output signal, the first output signal having a first level if the digital signal is higher than a preset threshold level, and a second level if the digital signal is not higher than the preset threshold level;
a second buffer gate unit configured to generate a second output signal, the second output signal having the first level if the level-reduced signal is higher than the preset threshold level, and the second level if the level-reduced signal is not higher than the preset threshold level;
a comparator unit configured to compare the first and second output signals to generate a comparison result indicating whether the first and second output signals agree with each other; and
a processing unit configured to determine whether a malfunction will soon occur, based on the comparison result.
2. The unit of claim 1, wherein
in a normal state, the level reduction unit reduces a level of the digital signal to set the level-reduced signal to a level higher than the preset threshold level; and
if the first and second output signals disagree with each other, the processing unit determines that the level of the digital signal has reduced and the malfunction will soon occur.
3. The unit of claim 2, wherein the processing unit receives a clock signal, measures a period preset based on the clock signal, and determines that the digital signal is interrupted if a state that the first and second output signals agree with each other and the digital signal is at a lower one of two preset levels is kept for the preset period.
4. The unit of claim 1, wherein
in a normal state, the level reduction unit reduces a level of the digital signal to set the level-reduced signal to a level lower than the preset threshold level; and
if the first and second output signals agree with each other, the processing unit determines that the level of the digital signal has increased and the malfunction will soon occur.
5. The unit of claim 4, wherein the processing unit receives a clock signal, measures a period preset based on the clock signal, and determines that the digital signal is interrupted if a state that the first and second output signals agree with each other and the digital signal is at a lower one of two preset levels is kept for the preset period.
6. A malfunction predicting unit comprising:
a level reduction unit configured to reduce an input digital signal by a preset level to generate a first level-reduced signal, and also configured to reduce the digital signal in a normal state to a level lower than a preset threshold level to generate a second level-reduced signal;
a first buffer gate unit configured to generate a first output signal, the first output signal having a first level if the digital signal is higher than the preset threshold level, and a second level if the digital signal is not higher than the preset threshold level;
a second buffer gate unit configured to generate a second output signal, the second output signal having the first level if the first level-reduced signal is higher than the preset threshold level, and the second level if the first level-reduced signal is not higher than the preset threshold level;
a third buffer gate unit configured to generate a third output signal, the second output signal having the first level if the second level-reduced signal is higher than the preset threshold level, and the second level if the second level-reduced signal is not higher than the preset threshold level;
a comparator unit configured to compare the first and second output signals to generate a first comparison result indicating whether the first and second output signals agree or disagree with each other, also configured to compare the first and third output signals to generate a second comparison result indicating whether the first and third output signals agree or disagree with each other; and
a processing unit configured to determine that a level of the digital signal has reduced and a malfunction will soon occur, if the first comparison result indicates that the first and second output signals disagree with each other, and also configured to determine that the level of the digital signal has increased and a malfunction will soon occur, if the second comparison result indicates that the first and third output signals agree with each other.
7. The unit of claim 6, wherein the processing unit performs:
receiving a clock signal;
measuring a period preset based on the clock signal;
determining that the digital signal is interrupted if a state that the first and second output signals agree with each other and the digital signal is at a lower one of two preset levels is kept for the preset period; and
determining that the digital signal is interrupted if a state that the first and third output signals agree with each other and the digital signal is at the lower level is kept for the preset period.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of performing selective electroless plating comprising:
providing a substrate having a first dielectric layer thereover;
forming an opening extending only partially through the first dielectric layer;
forming a single conductive material directly on and in physical contact with the first dielectric layer, the single conductive material entirely filling the opening;
forming a hydrogen rich target layer over the conductive material, the hydrogen rich target layer comprising a hydrogen rich nitride material containing greater than 3 atomic percent hydrogen:
forming an opening to form a contact on the conductive material; and
performing selective electroless plating of a thin film over the contact.
2. The method of claim 1 wherein the target layer is hydrogen rich dielectric.
3. The method of claim 1 wherein the target layer further comprises chlorine.
4. The method of claim 1 further comprising forming a second dielectric layer over the target layer, wherein the second dielectric layer is oxide based.
5. The method of claim 4 wherein the second dielectric layer is formed at a temperature less than 600\xb0 C.
6. The method of claim 1 wherein the second dielectric layer is hydrogen poor relative to the target layer.
7. The method of claim 1 further comprising performing a preclean prior to performing selective electroless plating.
8. The method of claim 1 wherein the thin film comprises one or more members of the group consisting of nickel, thallium, phosphorous, gold, silver, copper, cobalt, palladium, platinum, boron, rhodium, iron, tungsten, binary alloys of these metals and ternary alloys of these metals.
9. The method of claim 1 wherein the thin film comprises a ternary alloy of nickel, thallium and boron.
10. The method of claim 1 wherein the thin film comprises a ternary ally of nickel, phosphorous and copper.
11. The method of claim 1 wherein the first dielectric layer comprises one or more members of the group consisting of SiO2, doped SiO2, phosphosilicate glass, tetraethyl orthosilicate, silicon oxynitride and any non-conductive metal nitride.
12. The method of claim 1, wherein after formation of the first dielectric layer, a trench or via is formed in the first dielectric layer and wherein the conductive layer is formed within the via.
13. The method of claim 1 wherein the hydrogen rich target layer is formed over the conductive layer and over the first dielectric layer.
14. The method of claim 1 further comprising performing an activation pretreatment prior to the electroless plating, the pretreatment utilizing one or more of PdCl2 and a tin-zinc combination.
15. A method of depositing metal over a dielectric material, comprising:
forming a dielectric material over a substrate;
forming a first opening partially through the dielectric material;
depositing a conductive material to entirely fill the opening;
forming a hydrogen rich dielectric material containing greater than 3 atomic percent hydrogen and chlorine over and in direct contact with the conductive material;
forming a non-hydrogen rich dielectric containing no more than 3 atomic percent hydrogen over the hydrogen rich dielectric material;
forming a second opening extending through the non-hydrogen rich dielectric material and the hydrogen rich dielectric material; and
depositing a metal material within the second opening and in direct contact with the conductive material.
16. The method of claim 15 wherein the hydrogen rich dielectric material contains approximately 6 atomic percent hydrogen.
17. The method of claim 15 wherein the hydrogen rich dielectric material comprises an oxide.
18. The method of claim 15 wherein the non-hydrogen rich dielectric material comprises an oxide.