1. A surgical implantation procedure comprising:
while a spacer having an expandable member is disposed external to a patient, introducing a first fluid into the expandable member until the expandable member expands to a predetermined size corresponding to a predetermined spatial relation between adjacent spinous processes;
removing at least a portion of the first fluid from the expandable member to cause the expandable member to retract;
after removing the at least a portion of the first fluid, inserting the expandable member between the spinous processes;
thereafter, introducing a curable second fluid into the expandable member while the expandable member is disposed between the spinous processes; wherein the curable second fluid is introduced in an amount that causes the expandable member to re-expand to the predetermined size;
allowing the curable second fluid to cure while the expandable member is disposed between the spinous processes.
2. The procedure of claim 1 further comprising constraining the re-expansion of the expandable member to be in superior-inferior direction during the introduction of the second fluid.
3. The procedure of claim 1 further comprising sensing the pressure of the second fluid and terminating the re-expansion of the expandable member when the pressure reaches a predetermined value.
4. The procedure of claim 1 further comprising sensing when the re-expansion of the expandable member reaches a predetermined amount, and then terminating the re-expansion of the expandable member in response thereto.
5. The procedure of claim 1 wherein re-expanding the expandable member comprises introducing the second fluid into an interior of the expandable member, and sensing the pressure of the second fluid and terminating the re-expansion of the expandable member when the pressure reaches a predetermined value.
6. The procedure of claim 1 wherein re-expanding of the expandable member causes movement of the spinous processes away from each other.
7. A surgical implantation procedure comprising:
inserting an expandable member between two adjacent spinous processes;
introducing a first fluid into the expandable member such that the expandable member expands while being disposed between the adjacent spinous processes;
removing at least a portion of the first fluid from the expandable member to cause the expandable member to retract;
thereafter, introducing a curable second fluid into the expandable member to thereby cause the expandable member to re-expand while the expandable member is disposed between the spinous processes; and
allowing the curable second fluid to cure while the expandable member is disposed between the spinous processes.
8. The procedure of claim 7 wherein when the expandable member expands and re-expands, the expandable member is constrained in directions other than the superior-inferior direction.
9. The procedure of claim 7 further comprising measuring a characteristic of the first fluid that is required in order to achieve a desired distraction of the spinous processes.
10. The procedure of claim 9 wherein the characteristic of the first fluid is the pressure or volume of the first fluid.
11. The procedure of claim 7 further comprising sensing when the re-expansion of the expandable member reaches a predetermined amount, and then terminating the re-expansion of the expandable member in response thereto.
12. The procedure of claim 11 further comprising sensing the pressure of the second fluid and terminating the re-expansion of the expandable member when the re-expansion of the expandable member reaches the predetermined amount.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus, comprising:
a plurality of macrocells comprising logic capable of performing one or more functions;
a clock tree comprising a local branch within each macrocell, each local branch capable of receiving a first clock signal and providing at least one second clock signal to the corresponding macrocell; and
at least one glitch detection circuit capable of detecting a glitch in one or more of the second clock signals.
2. The apparatus of claim 1, wherein the at least one glitch detection circuit comprises:
a toggle source capable of providing a toggling signal; and
a plurality of registers, a first register capable of receiving and latching the toggling signal, each additional register capable of receiving and latching an output signal from a prior register.
3. The apparatus of claim 2, wherein:
each macrocell includes one or more of the registers; and
each macrocell is capable of clocking the one or more registers in the macrocell using the second clock signal provided by the local branch in the macrocell.
4. The apparatus of claim 3, wherein the at least one glitch detection circuit further comprises:
circuitry capable of comparing the latched signals from two or more of the registers to identify the glitch.
5. The apparatus of claim 4, wherein:
the plurality of registers comprises a plurality of D flip-flops; and
the circuitry capable of comparing the latched signals comprises an XNOR gate.
6. The apparatus of claim 5, wherein the XNOR gate is capable of receiving the latched signals from the D flip-flops in a last two of the macrocells.
7. The apparatus of claim 1, wherein the macrocells comprise components of a smartcard.
8. The apparatus of claim 7, wherein the macrocells comprise two or more different macrocells each selected from the group consisting of:
a modular arithmetic processor capable of executing asymmetrical cryptographic algorithms;
an encryption accelerator capable of executing symmetrical cryptographic algorithms;
a Cyclic Redundant Check module;
a timer;
a security administrator capable of detecting security violations;
a central processing unit; and
a serial interface.
9. The apparatus of claim 1, further comprising:
a clock generator capable of generating a clock signal; and
a filter capable of filtering the generated clock signal and providing the filtered clock signal to the clock tree as the first clock signal.
10. A secure device, comprising:
a memory capable of storing information; and
a secure microcontroller capable of securing the information in the memory, the secure microcontroller comprising:
a plurality of macrocells comprising logic capable of performing one or more functions;
a clock tree comprising a local branch within each macrocell, each local branch capable of receiving a first clock signal and providing at least one second clock signal to the corresponding macrocell; and
at least one glitch detection circuit capable of detecting a glitch in one or more of the second clock signals.
11. The secure device of claim 10, wherein the at least one glitch detection circuit comprises:
a toggle source capable of providing a toggling signal; and
a plurality of registers, a first register capable of receiving and latching the toggling signal, each additional register capable of receiving and latching an output signal from a prior register.
12. The secure device of claim 11, wherein:
each macrocell includes one or more of the registers; and
each macrocell is capable of clocking the one or more registers in the macrocell using the second clock signal provided by the local branch in the macrocell.
13. The secure device of claim 12, wherein the at least one glitch detection circuit further comprises:
circuitry capable of comparing the latched signals from two or more of the registers to identify the glitch.
14. The secure device of claim 13, wherein:
the plurality of registers comprises a plurality of D flip-flops; and
the circuitry capable of comparing the latched signals comprises an XNOR gate.
15. The secure device of claim 14, wherein the XNOR gate is capable of receiving the latched signals from the D flip-flops in a last two of the macrocells.
16. A method, comprising:
operating, in a secure device, a plurality of macrocells comprising logic capable of performing one or more functions, each macrocell receiving at least one clock signal from a local branch of a clock tree within the corresponding macrocell; and
during operation of the macrocells, detecting a glitch in one or more of the clock signals.
17. The method of claim 16, wherein detecting the glitch comprises:
generating a toggling signal; and
latching the toggling signal in a plurality of registers, a first register capable of receiving and latching the toggling signal, each additional register capable of receiving and latching an output signal from a prior register.
18. The method of claim 17, wherein each macrocell includes one or more of the registers, the method further comprising clocking the one or more registers in the macrocell using the clock signal provided by the local branch in the macrocell.
19. The method of claim 18, wherein detecting the glitch further comprises:
comparing the latched signals from two or more of the registers to identify the glitch.
20. The method of claim 19, wherein the plurality of registers comprises a plurality of D flip-flops, the method further comprising:
comparing the latched signals comprises providing the latched signals from the D flip-flops in a last two of the macrocells to an XNOR gate; and
latching an output of the XNOR gate, the latched output of the XNOR gate indicative of whether the glitch has been detected.