1. A system comprising:
a transmit side having a double-data rate (DDR) interface adapted to transfer data on both the rising and falling edges of a source clock signal, with data signals transferred on N single-ended data lines and a source clock signal transferred on a single-ended clock line, with the transmit side including:
a Tx phase-shifting block having N clock signal outputs, with the Tx phase-shifting block adapted to receive a 2\xd7 clock signal having double the frequency of the source clock signal, adapted to generate a plurality of phase-shifted Tx clock signals, with each phase-shifted Tx clock signal output by a corresponding clock signal output, and with successive phase-shifted Tx clock signals shifted in time by a different multiple of \u0394t relative to the received 2\xd7 clock signal;
a plurality of N output signal switching blocks, each coupled to a corresponding one of the N single-ended data lines and directly coupled to a clock signal output of the Tx phase-shifting block, adapted to receive a phase-shifted Tx clock signal output by the directly coupled clock signal output as a phase-shifted data-out Tx clock signal, where each output signal switching block is adapted to switch a single-ended phase-shifted DDR data signal onto the corresponding data line in synchronism with a coupled phase-shifted data-out Tx clock signal with switching of successive single-ended phase-shifted DDR data signals shifted in time by a different multiple of \u0394t relative to the 2\xd7 clock signal; and
a clock signal switching block, coupled to the Tx phase-shifting block and adapted to receive a single-ended phase-shifted Tx clock signal as a phase-shifted Tx clock signal, adapted to switch a single-ended Tx source clock signal onto the source clock line in synchronism with a received phase-shifted Tx clock signal;
a receive side, having a DDR interface, comprising:
a plurality of N input sampling blocks, each coupled to a corresponding one of the N single-ended signal lines, each sampling block adapted to sample a single-ended phase-shifted data signal from the corresponding data line in synchronism with a coupled compensated Rx clock signal; and
an Rx dynamic adjustment circuit, coupled to the N input sampling blocks, adapted to receive the single-ended phase-shifted Tx source clock signal and to generate a plurality of compensated Rx clock signals adjusted in phase to compensate for phase shifts introduced into corresponding single-ended phase-shifted DDR data signals at the transmit side, and adapted to couple a compensated Rx clock signal to each input latch to sample a corresponding single-ended phase-shifted DDR data signal.
2. The system of claim 1 where each output signal switching block comprises:
a multiplexor having data inputs coupled to receive first and second data signals, a control input coupled to receive a phase-shifted Tx data-out clock signal, and a data output; and
a latch having a data input coupled to the data output of the multiplexor and a clock input coupled to receive the phase-shifted data-out Tx clock signal.
3. The system of claim 1 where said Tx phase-shifting block comprises a phase-locked loop.
4. The system of claim 1 where said Tx phase-shifting block comprises a delay-locked loop.
5. A method comprising:
at a transmit side of the DDR interface that utilizes single-ended data lines and a single-ended source clock line:
phase-shifting a set of single-ended data signals to be transmitted relative to each other prior to transmission to form a set of phase-shifted single-ended data signals, with successive single-ended data signals shifted in time by a non-variable multiple of a fixed time interval;
phase-shifting a single-ended source clock signal relative to each single-ended data signal included in the set of single-ended data signals to form a phase-shifted source clock signal; and
transmitting the set of phase-shifted single-ended data signals and a phase-shifted source clock signal, with switching of successive phase-shifted single-ended data signals shifted in time by a different multiple of the fixed time interval relative to the single-ended source clock signal;
at a receive side of the DDR interface:
generating a set of phase-shifted receive clock signals based on a received phase-shifted source clock signal transmitted by the transmit side of the DDR interface with a phase-shift in each of the phase-shifted receive clock signals adjusted to compensate for the phase-shift in a corresponding phase-shifted single-ended data signal transmitted by the transmit side of the DDR interface; and
sampling each of the phase-shifted single-ended data signals transmitted by the transmit side of the DDR interface utilizing a corresponding phase-shifted receive clock signal to compensate for the phase shift introduced at the transmit side of the DDR interface.
6. A system comprising:
at a transmit side of a DDR interface that utilizes single-ended data lines and a single-ended source clock line:
means for phase-shifting a set of single-ended data signals to be transmitted relative to each other prior to transmission to form a set of phase-shifted single-ended data signals;
means for phase-shifting a single-ended source clock signal relative to each single-ended data signal included in the set of single-ended data signals to form a phase-shifted source clock signal, with successive single-ended data signals shifted in time by a non-variable multiple of a fixed time interval; and
means for transmitting the set of phase-shifted single-ended data signals and a phase-shifted source clock signal, with switching of successive phase-shifted single-ended data signals shifted in time by a different multiple of the fixed time interval relative to the single-ended source clock signal;
at a receive side of the DDR interface:
means for generating a set of phase-shifted receive clock signals based on a received phase-shifted source clock signal transmitted by the transmit side of the DDR interface with a phase-shift in each of the phase-shifted receive clock signals adjusted to compensate for the phase-shift in a corresponding phase-shifted single-ended data signal transmitted by the transmit side of the DDR interface; and
means for sampling each of the phase-shifted single-ended data signals transmitted by the transmit side of the DDR interface utilizing a corresponding phase-shifted receive clock signal to compensate for the phase shift introduced at the transmit side of the DDR interface.
7. The system of claim 6 where said means for phase-shifting comprises a phase-locked loop.
8. The system of claim 6 where said means for phase-shifting comprises a delay-locked loop.
9. A system comprising:
a transmit side having a double-data rate (DDR) interface adapted to transfer data on both the rising and falling edges of a source clock signal, with data signals transferred on N single-ended data lines and a source clock signal transferred on a single-ended clock line, with the transmit side including:
a Tx phase-shifting block having N clock signal outputs, with the Tx phase-shifting block adapted to receive a reference clock signal, and adapted to generate a plurality of phase-shifted Tx clock signals, with each phase-shifted Tx clock signal output by a corresponding clock signal output, and with successive phase-shifted Tx clock signals shifted in time by a different multiple of \u0394t relative to the received reference clock signal;
a plurality of N output signal switching blocks, each coupled to at least one corresponding single-ended data line in the set of single-ended data lines and directly coupled to a clock signal output of the Tx phase-shifting block adapted to receive a phase-shifted Tx clock signal output by the directly coupled clock signal output as a phase-shifted data-out Tx clock signal, where each output signal switching block is adapted to switch a single-ended phase-shifted DDR data signal onto at least one corresponding data line in synchronism with a coupled phase-shifted data-out Tx clock signal with switching of successive single-ended phase-shifted DDR data signals shifted in time by a different multiple of \u0394t relative to the 2\xd7 clock signal;
a clock signal switching block, coupled to the Tx phase-shifting block adapted to receive a single-ended phase-shifted Tx clock signal as a phase-shifted Tx clock signal, and adapted to switch a single-ended Tx source clock signal onto the source clock line in synchronism with a received phase-shifted Tx clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A closed kneader comprising:
a chamber for storing kneaded material;
a pressurizing lid for closing a top of said chamber; and
a pair of rotors installed in said chamber so as to oppose each other, each of said rotors comprising:
a rotor shaft, and
a rotor blade extending over a range on said rotor shaft from an end part on each of opposite sides of said rotor shaft to about a center of said rotor shaft;
wherein said rotor blade of each of said pair of rotors is tangentially mounted so as not to overlap one another; and
wherein a ratio of a rotor shaft radius to a radius of an inner face of said chamber is at least 0.65, a clearance between an outer circumferential face of said rotor shaft and an inner wall face of said chamber is no more than 35% of the radius of the inner face of said chamber, and a ratio of a land width of each said rotor blade to the rotor shaft radius is no more than 0.25.
2. A closed kneader comprising:
a kneader chamber having an open top and inner wall surfaces forming rotor receiving spaces in said kneader chamber;
a pressurizing cover to close said open top of said kneader chamber;
a first rotor comprising a rotor shaft having a rotor blade thereon, said first rotor being disposed in said kneader chamber and having a rotor shaft radius, and said rotor blade having a radially outer land thereon; and
a second rotor comprising a rotor shaft having a rotor blade thereon, said second rotor being disposed in said kneader chamber adjacent to said first rotor and having a rotor shaft radius, and said rotor blade having a radially outer land thereon;
wherein said rotor shaft radius of each of said first rotor and said second rotor has a ratio to a radius of one of said inner wall surfaces forming said rotor receiving spaces that is at least 0.65;
wherein a clearance between an outer circumferential face of each said rotor shaft and said inner wall faces of said chamber is no more than 35% of the radius of said inner wall faces of said chamber; and
wherein a ratio of a width of said land of said rotor blade of each of said first rotor and said second rotor to the rotor shaft radius is no more than 0.25.
3. The closed kneader of claim 2, wherein a circle defined by rotation of said rotor blade of said first rotor does not intersect with a circle defined by rotation of said rotor blade of said second rotor as seen in a direction along each said rotor shaft.
4. The closed kneader of claim 2, wherein said rotor blade of each of said first and second rotors comprises a first blade part that is axially and circumferentially spaced from a second blade part.