1. A control valve capable of being arranged inside a cylindrical receptacle, the control valve comprising:
a substantially cylindrical valve housing comprised of at least two axial subsections having ends that are open in a circumferential direction, stand opposite one another in the circumferential direction and bear one against the other;
a substantially cylindrical control piston arranged axially displaceably inside the valve housing; and
a securing ring, wherein at least one formfit element is formed on each of the at least two axial subsections so as to fasten the securing ring to the valve housing,
wherein each of the at least two axial subsections has an axial side face and on the axial side face at least one hook-shaped formfit element, which has a radially extending section, is formed, the at least one hook-shaped formfit element is open radially outward and engages behind the securing ring in an axial direction so that the securing ring bears both against the axial side face of each of the at least two axial subsections and against the radially extending section of the hook-shaped formfit element and holds the at least two axial subsections in position in relation to one another.
2. The control valve as claimed in claim 1, further comprising two axially spaced-apart axial stops formed on at least one of the at least two axial subsections for the control piston.
3. The control valve as claimed in claim 1, wherein the ends of the at least two axial subsections are connected to one another positively or in a materially integral way.
4. The control valve as claimed in claim 1, wherein at least one of the at least two axial subsections has a spring receptacle for receiving a spring element, which acts on the control piston.
5. The control valve as claimed in claim 1, wherein at least one of the at least two axial subsections has a nonreturn valve receptacle for a closing body of a nonreturn valve.
6. The control valve as claimed in claim 1, further comprising a sleeve bearing against an inner surface area of the valve housing and positioning elements formed on at least one of the at least two subsections, orientation of the sleeve in relation to the valve housing being defined by the positioning elements.
7. The control valve as claimed in claim 1, wherein the at least two axial subsections are produced from plastic.
8. The control valve as claimed in claim 1, wherein the securing ring defines a position of the valve housing in a receptacle of a camshaft.
9. The control valve as claimed in claim 1, wherein the at least two axial subsections are connected to one another pivotably by a thin material layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-32. (canceled)
33. A method of forming a multiple-gate field effect transistor (FET) structure comprising comprising:
providing a semiconductor substrate,
forming a gate region formed on said semiconductor substrate, said gate region comprising a gate portion and a channel portion, said gate portion having at least two opposite vertical surfaces adjacent to the channel portion;
forming a source region abutting said gate region at one end; and
forming a drain diffusion region abutting said gate region at the other end.
34. The method of claim 33, wherein said channel portion comprises either a Si channel, a strained-Si channel, a relaxed-SiGe channel, a strained-SiGe channel, a relaxed-Ge channel, a strained-Ge channel, or a SiC channel.
35. The method of claim 33, wherein said channel portion comprises a center relaxed-semiconductor material region and an outer strained-semiconductor material region that covers at least the two opposite vertical surfaces of the center relaxed-semiconductor material region.
36. The method of claim 35, wherein said center relaxed-semiconductor material is either a relaxed-Si, a relaxed-SiGe, or a relaxed-SiC, and said outer strained-semiconductor material comprises either strained-Si, strained-SiGe, strained-SiC or strained-Ge material, and said semiconductor substrate comprises Si, SiGe, SiC, Ge, GaN, GaAs or other III-V materials.
37. The method of claim 33, wherein said semiconductor substrate comprises a bulk Si substrate.
38. The method of claim 34, wherein said semiconductor substrate comprises an insulating substrate.
39. The method of claim 38, wherein said insulating substrate comprises an insulating layer of one of the following material: an SOI material, an SSOI (strained-Si on insulator) material, an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe on insulator) material, a GOI (Ge on insulator) material, or a strained-GOI (strained-Ge on insulator) material.
40. The method of claim 33, wherein said gate portion further comprises a conducting material film and an insulating film, said insulating film having at least two opposite vertical surfaces adjacent to the channel regions and separating said gate conductor from said channel portion.
41. The method of claim 33, wherein said gate portion comprises a metal-gate material.
42. The multiple-gate FET structure of claim 41, wherein said insulating film comprises a high-k dielectric material.
43. The method of claim 33, wherein said high-k dielectric material comprises HfO.
44. A method of forming a multiple-gate field effect transistor (FET) structure comprising:
providing a semiconductor substrate,
forming a gate region formed on said semiconductor substrate, said gate region comprising a gate portion and a channel portion, said gate portion having at two opposite vertical surface and one horizontal top surface adjacent to the channel portion; and
forming a source region abutting said gate region at one end; and
forming a drain diffusion region abutting said gate region at the other end.
45. The method of claim 44, wherein said channel portion comprises either a Si channel, a strained-Si channel, a relaxed-SiGe channel, a strained-SiGe channel, a relaxed-Ge channel, a strained-Ge channel, or a SiC channel.
46. The method of claim 44, wherein said channel portion comprises a center relaxed-semiconductor material region and an outer strained-semiconductor material region that covers at least the two opposite vertical surfaces of the center relaxed-semiconductor material region.
47. The method of claim 46, wherein said center relaxed-semiconductor material is either a relaxed-Si, a relaxed-SiGe, or a relaxed-SiC, and said outer strained-semiconductor material comprises either strained-Si, strained-SiGe, strained-SiC or strained-Ge material, and said semiconductor substrate comprises Si, SiGe, SiC, Ge, GaN, GaAs or other III-V materials.
48. The method of claim 44, wherein said semiconductor substrate comprises a bulk Si substrate.
49. The method of claim 44, wherein said semiconductor substrate comprises an insulating substrate.
50. The method of claim 49, wherein said insulating substrate comprises an insulating layer of one of the following material: an SOI material, an SSOI (strained-Si on insulator) material, an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe on insulator) material, a GOI (Ge on insulator) material, or a strained-GOI (strained-Ge on insulator) material.
51. The method of claim 44, wherein said gate portion further comprises a conducting material film and an insulating film, said insulating film having at least two opposite vertical surfaces adjacent to the channel regions and separating said gate conductor from said channel portion.
52. The method of claim 44, wherein said gate portion comprises a metal-gate material.
53. The method of claim 51, wherein said insulating film comprises a high-k dielectric material.
54. A method of forming a digitalized semiconductor structure comprising:
providing a semiconductor substrate; and
forming a plurality of fin-shaped strips formed on said semiconductor substrate, said fin-shaped strips having identical widths and identical heights and being distributed evenly throughout the entire substrate, with a feature pitch d between one another.
55. The method of claim 54, wherein each of said fin-shaped strips comprises a width and a height ranging between 1 nm and 200 nm.
56. The method of claim 54, wherein said pitch d comprises a range between 5 nm and 500 nm.
57. The method of claim 54, wherein said semiconductor substrate comprises a bulk Si substrate.
58. The method of claim 54, wherein said semiconductor substrate comprises an insulating substrate.
59. The method of claim 58, wherein said insulating substrate comprises an insulating layer of one of the following material: an SOI material, an SSOI (strained-Si on insulator) material, an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe on insulator) material, a GOI (Ge on insulator) material, or a strained-GOI (strained-Ge on insulator) material.
60. The method of claim 54, wherein said fin-shaped strips comprise either Si, strained-Si, relaxed-SiGe, strained-SiGe, relaxed-Ge, strained-Ge, SiC, or a semiconductor comprising of more than one material.
61. The method of claim 60, wherein said semiconductor comprises a center relaxed-semiconductor material region and an outer strained-semiconductor material region that covers at least the two opposite vertical surfaces of the center relaxed-semiconductor material region.
62. The method of claim 61, wherein said center relaxed-semiconductor material comprises either a relaxed-Si, a relaxed-SiGe, or a relaxed-SiC, and said outer strained-material comprises either strained-Si, strained-SiGe, strained-SiC or strained-Ge material.
63. The method of claim 61, wherein said outer strained-semiconductor material region further covers the horizontal top surfaces of the center relaxed-semiconductor material region.
64. A method of forming a digitalized semiconductor structure comprising:
providing a semiconductor substrate;
forming a first semiconductor layer on said substrate;
forming a second semiconductor layer on said first semiconductor layer, and said second semiconductor layer is different from said first semiconductor layer;
patterning said second semiconductor layer into a plurality of fin-shaped strips, said fin-shaped strips having identical heights, identical widths, and being distributed evenly throughout the entire substrate, with a feature pitch d between one another; and
converting said first semiconductor layer into a buried oxide layer.
65. The method of claim 64, wherein said semiconductor substrate comprises a Si substrate, or a SiGe virtual substrate with a relaxed SiGe film on a top layer.
66. The method of claim 64, wherein said first layer comprises either a Si layer, a strained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, a relaxed-Ge layer, a strained-Ge layer, or a SiC layer.
67. The method of claim 64, wherein said second layer comprises either a Si layer, a strained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, a relaxed-Ge layer, a strained-Ge layer, or a SiC layer, and said first layer is different from said second layer by different material or by different doping type.
68. The method of claim 64, wherein said first layer comprises a faster oxidation or nitridation rate than the second layer, and said first layer is converted into a buried oxide layer by selectively oxidation or nitridation.
69. The method in claim 64, wherein said first layer comprises faster etch rate than the second layer, and said first layer is converted into a buried oxide layer by selectively etching away the first layer and then the empty spaces are fill with insulator.
70. The method of claim 64 further comprising forming multiple-gate FET devices on the structure.
71. A method of forming a digitalized semiconductor structure comprising:
providing a semiconductor substrate;
forming a first semiconductor layer on said substrate;
converting said first semiconductor layer into a first porous semiconductor layer;
forming a second semiconductor layer on said first porous semiconductor layer;
patterning said second semiconductor layer into a plurality of fin-shaped strips, said fin-shaped strips having identical heights, identical widths, and being distributed evenly throughout the entire substrate, with a feature pitch d between one another; and
converting said first porous semiconductor layer into a buried oxide layer.
72. The method of claim 71, wherein said semiconductor substrate comprises a Si substrate or a SiGe virtual substrate with a relaxed SiGe film on a top layer.
73. The method of claim 71, wherein said first layer comprises either a Si layer, a strained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, a relaxed-Ge layer, a strained-Ge layer, or a SiC layer.
74. The method of claim 71, wherein said second layer comprises either a Si layer, a strained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, a relaxed-Ge layer, a strained-Ge layer, or a SiC layer.
75. The method in claim 71, wherein said first porous semiconductor layer is converted into a buried oxide layer by selectively oxidizing said first porous layer.
76. The method in claim 71 wherein said first porous semiconductor layer is converted into a buried oxide layer by selectively etching away said first porous layer and then the empty spaces are filled with oxide.
77. The method in claim 71 further comprising forming multiple-gate FET devices on the structure.