What is claimed is:
1. An apparatus for adjusting the level of a received signal strength (RSSI) according to temperature variation in a communication terminal, comprising:
an average power detector for detecting an average power of a received signal;
an RSSI compensation value detector for detecting an internal temperature of the RSSI compensation apparatus and detecting an RSSI compensation value according to the detected temperature; and
an RSSI detector for detecting an RSSI by adding the average power to the RSSI compensation value.
2. The apparatus as claimed in claim 1, wherein the average power detector comprises:
an analog-to-digital (AD) converter for converting an analog input signal to a digital signal;
a filter for filtering a signal output from the AD converter;
an average power detecting unit for detecting average power of the filtered signal;
and
a dBm converter for converting the detected average power to a dBm value.
3. The apparatus as claimed in claim 1, wherein the RSSI compensation value detector comprises:
a temperature detector for detecting a voltage corresponding to the internal temperature of the RSSI compensation apparatus;
an AD converter for converting the detected voltage to a digital signal;
a power error detector for detecting a power error corresponding to the converted digital signal; and
a dBm converter for converting the detected power error to a dBm value.
4. The apparatus as claimed in claim 3, wherein the temperature detector comprises a thermistor.
5. The apparatus as claimed in claim 3, wherein the power error detector comprises a compensation table in which RSSI compensation values are mapped according to the temperature.
6. The apparatus as claimed in claim 1, wherein the RSSI detector comprises:
an adder for adding the average power to the RSSI compensation value; and
an RSSI mapper for mapping the RSSI corresponding to the added value.
7. A method for compensating an RSSI according to temperature, comprising the steps of:
detecting average power of a received signal;
detecting an internal temperature of an RSSI compensation apparatus and detecting an RSSI compensation value according to the detected temperature; and
detecting an RSSI by adding the average power to the RSSI compensation value.
8. The method as claimed in claim 7, wherein the average power detecting step comprises the steps of:
converting an analog input signal to a digital signal;
filtering the converted digital signal to detect average power; and
converting the detected average power to a dBm value.
9. The method as claimed in claim 7, wherein the RSSI compensation value detecting step comprises the steps of:
detecting a voltage corresponding to the internal temperature of the RSSI compensation apparatus;
converting the detected voltage to a digital signal;
detecting a power error corresponding to the converted digital signal; and
converting the detected power error to a dBm value.
10. The method as claimed in claim 9, wherein the power error is detected from a compensation table in which RSSI compensation values are mapped according to the temperature.
11. The method as claimed in claim 7, wherein the RSSI detecting step comprises the steps of:
adding the average power to the RSSI compensation value; and
mapping the RSSI corresponding to the added value.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A semiconductor memory, comprising:
a memory cell array including dynamic memory cells;
an output connection operatively connected to said memory cell array for outputting data values stored in said dynamic memory cells;
a state machine selectively having an operating state selected from the group consisting of Read, Write and Refresh and having a signal connection providing a control signal for displaying the operating state Read;
a delay locked loop operatively connected to said state machine, said delay locked loop receiving an input clock signal and providing a delayed output clock signal, said delay locked loop having a signal connection for receiving the control signal from said state machine, said delay locked loop being configured to be actuated by the control signal in order to suppress a change in a delay time between the input clock signal and the delayed output clock signal during the operating state Read; and
an output driver operatively connected to said delay locked loop, said output driver being configured to be actuated by the delayed output clock signal in order to provide, at said output connection, data values read from said dynamic memory cells in sync with the delayed output clock signal.
2. The semiconductor memory according to claim 1, including a data signal path, said output driver being coupled to said dynamic memory cells via said data signal path for providing the data values read from said memory cells at said output connection.
3. The semiconductor memory according to claim 2, wherein the delayed output clock signal has a rising edge and a falling edge, said output driver provides, at said output connection, the data values read from said dynamic memory cells in sync with one of the rising edge and the falling edge of the delayed output clock signal.
4. The semiconductor memory according to claim 1, wherein said dynamic memory cells each include a transistor and a capacitor coupled to said data signal path via said transistor.
5. The semiconductor memory according to claim 1, wherein:
said state machine is configured to receive an address representing one of said dynamic memory cells and an operating command, the address and the operating command are provided as external signals; and
said state machine adopts a current operating state based on a preceding operating state, on the address representing said one of said dynamic memory cells, and on the operating command.
6. The semiconductor memory according to claim 1, wherein:
said delay locked loop has an input connection, an output connection, and a signal section with a controllable delay time, said signal section is connected between said input connection of said delay locked loop and said output connection of said delay locked loop;
said delay locked loop has a delay element having an input connected to said output; connection of said delay locked loop, a phase detector connected, on an input side thereof, to said input connection of said delay locked loop and to an output of said delay element, and said delay locked loop has a filter having an input connected to said phase detector and said filter has an output connected to said signal section for controlling a delay time; and
said delay locked loop is configured such that a change of the controllable delay time of said signal section is selectively turned on and turned off via said signal connection of said delay locked loop.
7. The semiconductor memory according to claim 6, including:
first circuit elements connected between a connection for the input clock signal and said input connection of said delay locked loop, said first circuit elements having a delay time;
second circuit elements connected between said output connection of said delay locked loop and said output driver, said second circuit elements having a delay time; and
said delay element has a delay time coupled to the delay time of said first circuit elements and to the delay time of said second circuit elements in order to synchronize the input clock signal with the data values read out at said output connection operatively connected to said memory cell array for outputting the data values stored in said dynamic memory cells.